公开(公告)号：US06498100B2

公开(公告)日：2002-12-24

申请号：US09996918

申请日：2001-11-30

申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

公开(公告)号：US06204184B1

公开(公告)日：2001-03-20

申请号：US09276969

申请日：1999-03-26

申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, the insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

摘要翻译： 在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽 场区域和半导体衬底。 然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻将绝缘膜部分地从存储垫部分除去。 在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。 能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。 同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使 可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

公开(公告)号：US06380085B2

公开(公告)日：2002-04-30

申请号：US09750061

申请日：2000-12-29

申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

摘要翻译： 在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽 场区域和半导体衬底。 然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻部分地从存储垫部分去除绝缘膜。 在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。 能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。 同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使 可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

公开(公告)号：US06953728B2

公开(公告)日：2005-10-11

申请号：US10775236

申请日：2004-02-11

申请人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

发明人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

IPC分类号： H01L29/43 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10873

摘要： This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

摘要翻译： 该半导体器件制造方法包括以下步骤：在衬底的第一区域形成厚栅氧化膜（厚氧化物膜），在第二区域形成薄的栅极氧化膜（薄氧化物层），然后施加氧氮化 到这些栅氧化膜; 在这些栅极氧化膜上形成栅电极至1d; 以及在形成栅电极的步骤之前或之后，将含有氮或氮原子的离子注入到所述堰栅氧化膜（厚氧化物膜）和所述衬底之间的界面的至少一部分中，从而形成高度氧氮化 地区。 以这种方式，在并入具有薄栅极绝缘膜的MISFET和具有厚栅极绝缘膜的MISFET的半导体器件中，具有厚栅极绝缘膜的MISFET的热载流子可靠性得到改善。

公开(公告)号：US06727146B2

公开(公告)日：2004-04-27

申请号：US10288448

申请日：2002-11-06

申请人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

发明人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10873

摘要： This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

摘要翻译： 该半导体器件制造方法包括以下步骤：在衬底的第一区域形成厚栅氧化膜（厚氧化物膜），在第二区域形成薄的栅极氧化膜（薄氧化物层），然后施加氧氮化 到这些栅氧化膜; 在这些栅极氧化膜上形成栅电极至1d; 以及在形成栅电极的步骤之前或之后，将含有氮或氮原子的离子注入到所述堰栅氧化膜（厚氧化物膜）和所述衬底之间的界面的至少一部分中，从而形成高度氧氮化 地区。 以这种方式，在并入具有薄栅极绝缘膜的MISFET和具有厚栅极绝缘膜的MISFET的半导体器件中，具有厚栅极绝缘膜的MISFET的热载流子可靠性得到改善。

公开(公告)号：US06677194B2

公开(公告)日：2004-01-13

申请号：US10162573

申请日：2002-06-06

申请人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

发明人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L21/823842 ,  H01L21/823892

摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

摘要翻译： 低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。 使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。 栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。 可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。 这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

公开(公告)号：US5270232A

公开(公告)日：1993-12-14

申请号：US943018

申请日：1992-09-10

申请人： Shinichiro Kimura ,  Shoji Shukuri ,  Hiromasa Noda ,  Digh Hisamoto ,  Hideyuki Matsuoka ,  Kazuyoshi Torii ,  Natsuki Yokoyama ,  Toshiyuki Yoshimura ,  Kazunori Tsujimoto ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Shoji Shukuri ,  Hiromasa Noda ,  Digh Hisamoto ,  Hideyuki Matsuoka ,  Kazuyoshi Torii ,  Natsuki Yokoyama ,  Toshiyuki Yoshimura ,  Kazunori Tsujimoto ,  Eiji Takeda

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/70

CPC分类号： H01L29/66606 ,  H01L21/28525 ,  H01L29/66621 ,  Y10S438/947

摘要： A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.

摘要翻译： 在基板上形成绝缘体膜和导体层的开口处形成非常薄的氧化膜，并且在开口的侧壁上形成含杂质的多晶硅。 通过非常薄的氧化膜从硅到衬底的杂质扩散导致扩散杂质的有效浓度降低，导致形成较浅的源/漏区。 此后，在由形成在开口的侧壁上的绝缘膜限定的区域中的基板表面上形成栅绝缘膜和栅电极。 小于开口的栅极电极，其尺寸对应于处理极限，并且较浅的源极/漏极区域提供小型化的MOSFET。

公开(公告)号：US07196368B2

公开(公告)日：2007-03-27

申请号：US10914223

申请日：2004-08-10

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线， 选择线。 由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触， 外围电路区域和存储单元区域之间的台阶高度显着降低。

公开(公告)号：US06798005B2

公开(公告)日：2004-09-28

申请号：US10206215

申请日：2002-07-29

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小， 随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触 （33），外围电路区域和存储单元区域之间的台阶高度显着降低。

公开(公告)号：US6130449A

公开(公告)日：2000-10-10

申请号：US943592

申请日：1997-10-03

申请人： Hideyuki Matsuoka ,  Shinichiro Kimura ,  Toshiaki Yamanaka

发明人： Hideyuki Matsuoka ,  Shinichiro Kimura ,  Toshiaki Yamanaka

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01L29/40 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10882 ,  H01L27/10894 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

摘要： A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array region is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed, therefore a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied, besides interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, stuffing of metal in the holes and the like are unnecessary and as a result reliability of the process is improved.

摘要翻译： 提供一种半导体存储器件及其制造方法，其中仅在外围电路区域之上形成仅覆盖存储单元阵列区域的外围电路区域的层间膜，以减少位线之后的两个区域之间的拓扑差异 因此，以普通表面为主要的半导体衬底可以用作起始体，而不需要预处理，并且还可以应用浅沟槽隔离技术，除了与外围电路的互连之外，还可以引导到 通过多级插头连接装置的表面，从而处理大的纵横比孔，在孔中填充金属等，从而提高了工艺的可靠性。