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公开(公告)号：US11424830B2
公开(公告)日：2022-08-23
申请号：US17014665
申请日：2020-09-08
Applicant: Ayar Labs, Inc.
Inventor： Chen Sun , Roy Edward Meade , Mark Wade , Alexandra Wright , Vladimir Stojanovic , Rajeev Ram , Milos Popovic , Derek Van Orden
IPC: G02B6/12 , H04B10/50 , H01S5/40 , H01S5/026 , H04J14/02 , H01S5/02325 , H01S5/50 , H01S5/024 , H01S4/00
Abstract: A laser module includes a laser source and an optical marshalling module. The laser source is configured to generate and output a plurality of laser beams. The plurality of laser beams have different wavelengths relative to each other. The different wavelengths are distinguishable to an optical data communication system. The optical marshalling module is configured to receive the plurality of laser beams from the laser source and distribute a portion of each of the plurality of laser beams to each of a plurality of optical output ports of the optical marshalling module, such that all of the different wavelengths of the plurality of laser beams are provided to each of the plurality of optical output ports of the optical marshalling module. An optical amplifying module can be included to amplify laser light output from the optical marshalling module and provide the amplified laser light as output from the laser module.
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公开(公告)号：US20220214497A1
公开(公告)日：2022-07-07
申请号：US17701072
申请日：2022-03-22
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Chen Sun , Shahab Ardalan , John Fini , Forrest Sedgwick
Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
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公开(公告)号：US20220148627A1
公开(公告)日：2022-05-12
申请号：US17583967
申请日：2022-01-25
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Vladimir Stojanovic , Chen Sun , Mark Wade , Hugo Saleh , Charles Wuischpard
Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.
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公开(公告)号：US11137548B2
公开(公告)日：2021-10-05
申请号：US16683123
申请日：2019-11-13
Applicant: Ayar Labs, Inc.
Inventor： John Fini , Roy Edward Meade , Derek Van Orden , Forrest Sedgwick
Abstract: A grating coupler reflector (retro reflector) is formed within a photonics chip and includes a vertical scattering region, an optical waveguide, and a reflector. The optical waveguide is optically coupled to the vertical scattering region. The reflector is positioned at an end of the optical waveguide. The reflector is configured to reflect light that propagates through the optical waveguide from the vertical scattering region back toward the vertical scattering region. The location of the grating coupler reflector on the photonics chip is determinable by scanning a light emitting active optical fiber over the chip and detecting when light is reflected back into the active optical fiber from the grating coupler reflector. The determined location of the grating coupler reflector on the photonics chip is usable as a reference location for aligning optical fiber(s) to corresponding optical grating couplers on the photonics chip.
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公开(公告)号：US11101912B2
公开(公告)日：2021-08-24
申请号：US16510824
申请日：2019-07-12
Applicant: Ayar Labs, Inc.
Inventor： Vladimir Stojanovic , Alexandra Wright , Chen Sun , Mark Wade , Roy Edward Meade
Abstract: A TORminator module is disposed with a switch linecard of a rack. The TORminator module receives downlink electrical data signals from a rack switch. The TORminator module translates the downlink electrical data signals into downlink optical data signals. The TORminator module transmits multiple subsets of the downlink optical data signals through optical fibers to respective SmartDistributor modules disposed in respective racks. Each SmartDistributor module receives multiple downlink optical data signals through a single optical fiber from the TORminator module. The SmartDistributor module demultiplexes the multiple downlink optical data signals and distributes them to respective servers. The SmartDistributor module receives multiple uplink optical data signals from multiple servers and multiplexes them onto a single optical fiber for transmission to the TORminator module. The TORminator module coverts the multiple uplink optical data signals to multiple uplink electrical data signals, and transmits the multiple uplink electrical data signals to the rack switch.
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Patent Agency Ranking
公开(公告)号：US11101617B2
公开(公告)日：2021-08-24
申请号：US16513661
申请日：2019-07-16
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade
Abstract: A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.
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公开(公告)号：US20210109284A1
公开(公告)日：2021-04-15
申请号：US17070601
申请日：2020-10-14
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Chong Zhang , Haiwei Lu , Chen Li
Abstract: A multi-chip package assembly includes a substrate, a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. An optical fiber assembly including the plurality of optical fibers is positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector located at a distal end of the optical fiber assembly.
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公开(公告)号：US20200382215A1
公开(公告)日：2020-12-03
申请号：US16995816
申请日：2020-08-18
Applicant: Ayar Labs, Inc.
Inventor： Chen Sun , Roy Edward Meade , Mark Wade , Alexandra Wright , Vladimir Stojanovic , Rajeev Ram , Milos Popovic , Derek Van Orden , Michael Davenport
Abstract: An interposer device includes a substrate that includes a laser source chip interface region, a silicon photonics chip interface region, an optical amplifier module interface region. A fiber-to-interposer connection region is formed within the substrate. A first group of optical conveyance structures is formed within the substrate to optically connect a laser source chip to a silicon photonics chip when the laser source chip and the silicon photonics chip are interfaced to the substrate. A second group of optical conveyance structures is formed within the substrate to optically connect the silicon photonics chip to an optical amplifier module when the silicon photonics chip and the optical amplifier module are interfaced to the substrate. A third group of optical conveyance structures is formed within the substrate to optically connect the optical amplifier module to the fiber-to-interposer connection region when the optical amplifier module is interfaced to the substrate.
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公开(公告)号：US10775576B2
公开(公告)日：2020-09-15
申请号：US16287984
申请日：2019-02-27
Applicant: Ayar Labs, Inc.
Inventor： Roy Edward Meade , Vladimir Stojanovic
Abstract: A plurality of lid structures include at least one lid structure configured to overlie one or more heat sources within a multi-chip-module and at least one lid structure configured to overlie one or more temperature sensitive components within the multi-chip-module. The plurality of lid structures are configured and positioned such that each lid structure is separated from each adjacent lid structure by a corresponding thermal break. A heat spreader assembly is positioned in thermally conductive interface with the plurality of lid structures. The heat spreader assembly is configured to cover an aggregation of the plurality of lid structures. The heat spreader assembly includes a plurality of separately defined heat transfer members respectively configured and positioned to overlie the plurality of lid structures. The heat spreader assembly is configured to limit heat transfer between different heat transfer members within the heat spreader assembly.
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公开(公告)号：US20200158959A1
公开(公告)日：2020-05-21
申请号：US16685838
申请日：2019-11-15
Applicant: Ayar Labs, Inc.
Inventor： Shahab Ardalan , Michael Davenport , Roy Edward Meade
Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.
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