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    Network processor interface for building scalable switching systems
    71.
    发明授权
    Network processor interface for building scalable switching systems 失效
    用于构建可扩展交换系统的网络处理器接口

    公开(公告)号：US06868082B1

    公开(公告)日：2005-03-15

    申请号：US09385603

    申请日：1999-08-30

    申请人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Santosh Prasad Gaur ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Santosh Prasad Gaur ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： G06F13/28 ,  G06F13/40 ,  H04L12/28

    CPC分类号： G06F13/4022

    摘要： A network apparatus comprising storage units storing configuration information about the network apparatus, an input network interface to at least one network physical line, at least one processor receiving network data from said network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units, a first bus interface to two bus connections, a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface, a second bus interface to two bus connections, an output network interface to at least one network physical line, a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage units, said at least one processor reading said formatted data units from said storage units, processing them and sending them as network data to at least one network physical line through said output network interface. On the basis of this network processor, it is possible to build switching systems by adding one network processor and at least one switch; it is also possible to build double density blades attached to two redundant switch fabrics which can also be accessed concurrently.

    摘要翻译： 一种网络装置，包括存储关于网络装置的配置信息的存储单元，至少一个网络物理线路的输入网络接口，至少一个处理器，从所述网络接口接收网络数据，处理所述数据，将关于所述网络数据的信息存储在所述 存储单元，将所述数据作为格式化数据单元存储在所述存储单元中，到两个总线连接的第一总线接口，读取所述配置信息的第一硬件组件和关于存储在所述存储单元中的数据的所述信息，以及控制所存储的所述格式化数据单元 所述存储单元到所述第一总线接口的两个总线连接中的至少一个，到两个总线连接的第二总线接口，到至少一个网络物理线的输出网络接口，第二硬件组件读取到达 所述第二总线接口的两个总线连接中的至少一个，并存储所述格式化的数据 所述至少一个处理器从所述存储单元读取所述格式化的数据单元，处理它们并通过所述输出网络接口将它们作为网络数据发送到至少一个网络物理线路。 在该网络处理器的基础上，可以通过添加一个网络处理器和至少一个交换机构建交换系统; 也可以构建连接到两个冗余交换结构的双密度刀片，这两个冗余交换机也可以同时访问。

    Method and system for network processor scheduling based on calculation
    73.
    发明授权
    Method and system for network processor scheduling based on calculation 失效
    基于计算的网络处理器调度方法与系统

    公开(公告)号：US06804249B1

    公开(公告)日：2004-10-12

    申请号：US09548911

    申请日：2000-04-13

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L1256

    CPC分类号： H04L47/28 ,  H04L45/02 ,  H04L47/2441 ,  H04L47/50 ,  H04L2012/5681

    摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on minimum bandwidth specifications where position in the queue is adjusted after each service based on minimum bandwidth specificaiton and the length of frame, a process which is subject to rounding errors. To avoid the accumulation of rounding errors inequitably influencing the position of some in the queue, a system to adjust for the rounding errors adds an increased measure of fairness to the system.

    摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于基于最小带宽规范来调度来自网络处理单元的处理的信息单元（或帧）的处理的信息单元（或帧），其中基于最小带宽规定在每个服务之后调整队列中的位置，并且 帧的长度，一个进行舍入误差的过程。 为了避免累积误差不均衡地影响队列中某些队员的位置，调整舍入误差的系统增加了系统的公平性。

    Method and system for network data flow management with improved completion unit
    75.
    发明授权
    Method and system for network data flow management with improved completion unit 失效
    网络数据流管理方法与系统改进完成单元

    公开(公告)号：US06633920B1

    公开(公告)日：2003-10-14

    申请号：US09479028

    申请日：2000-01-07

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Steven Kenneth Jenkins ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Steven Kenneth Jenkins ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： G06F1300

    CPC分类号： H04L29/06 ,  H04L69/18 ,  H04L69/22

    摘要： A system and method of data flow management, particularly in a multiple network processor architecture where a plurality of independent processing units are simultaneously processing information from different frames of input information. The present invention includes first-in-first-out files identifying the individual frames and correlating the frames with the processor to which the frames have been assigned for processing as well as a first-in-first-out file of processed frames for each processor to allow the frames to be processed independently, then reassembled into the same order as the frames had been received without communication between the independent processors. Additionally, the present system supports newly-created frames as well as the concept of flushing the system without regard to frame order whereby frames are sent out to the network as the processing is completed without regard to input order, overriding the system of putting the output frames in the same order as the input frames were received from the network.

    摘要翻译： 特别是在多个独立处理单元同时处理来自不同输入信息帧的信息的多网络处理器架构中的数据流管理系统和方法。 本发明包括识别各个帧的先进先出文件，并且将帧与已被分配帧进行处理的处理器相关联，以及每个处理器的处理帧的先进先出文件 以允许帧被独立地处理，然后重新组装成与已经被接收的帧相同的顺序，而没有独立处理器之间的通信。 此外，本系统支持新创建的帧以及刷新系统的概念，而不考虑帧顺序，由此在不考虑输入顺序的情况下处理完成而将帧发送到网络，覆盖输出的系统 与从网络接收输入帧相同顺序的帧。

    Cycle saving technique for managing linked lists
    76.
    发明授权
    Cycle saving technique for managing linked lists 失效
    用于管理链表的循环保存技术

    公开(公告)号：US06584518B1

    公开(公告)日：2003-06-24

    申请号：US09479751

    申请日：2000-01-07

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    IPC分类号： G06F1314

    CPC分类号： G06F12/023

    摘要： A method and system for queueing data within a data storage device including a set of storage blocks each having an address, a pointer field, and a data field. This set of storage blocks comprises a linked list of associated storage blocks and also a free pool of available storage blocks. The storage device further includes a tail register for tracking an empty tail block from which a data object is enqueued into the linked list. A request to enqueue a data object into the linked list is received within the data storage system. In response to the data enqueue request, an available storage block from the free pool is selected and associated with the tail register. A single write operation is then required to write the data object into the data field of a current tail block and to write the address of the selected storage block into the pointer field of the current tail block, such that the selected storage block becomes a new tail block to which the tail register points.

    摘要翻译： 一种用于在数据存储设备内排队数据的方法和系统，包括一组存储块，每个存储块具有地址，指针字段和数据字段。 这组存储块包括相关联的存储块的链表以及可用存储块的空闲池。 存储装置还包括用于跟踪空尾部块的尾部寄存器，数据对象从该尾部块排入链接列表。 在数据存储系统内接收到将数据对象排入链表的请求。 响应于数据排入请求，从空闲池中选择一个可用的存储块并将其与尾部寄存器相关联。 然后需要单个写入操作来将数据对象写入当前尾部块的数据字段，并将所选择的存储块的地址写入当前尾部块的指针字段，使得所选择的存储块变为新的 尾部寄存器指向的尾部块。

    Methods, systems and computer program products for suppressing multiple destination traffic in a computer network
    79.
    发明授权
    Methods, systems and computer program products for suppressing multiple destination traffic in a computer network 失效
    用于抑制计算机网络中的多个目标流量的方法，系统和计算机程序产品

    公开(公告)号：US06185185B2

    公开(公告)日：2001-02-06

    申请号：US08976430

    申请日：1997-11-21

    申请人： Brian Mitchell Bass ,  Michael Steven Siegel ,  Norman Clark Strole

    发明人： Brian Mitchell Bass ,  Michael Steven Siegel ,  Norman Clark Strole

    IPC分类号： H04L1226

    CPC分类号： H04L12/1886 ,  H04L47/12 ,  H04L47/15 ,  H04L47/2441 ,  H04L47/32

    摘要： Methods, systems and computer program products are provided which control message storms in a network by classifying multiple destination messages into a plurality of broadcast message classes based upon characteristics of the broadcast messages. The number of multiple destination messages for each class of broadcast messages of the plurality of classes of broadcast messages are then counted so as to provide a plurality of broadcast message class counts. Multiple destination messages of a class of broadcast messages are then selectively transmitted based upon the broadcast message class count for the class of broadcast messages.

    摘要翻译： 提供方法，系统和计算机程序产品，其通过基于广播消息的特征将多个目的地消息分类为多个广播消息类别来控制网络中的消息风暴。 然后对多个广播消息类的每个类别的广播消息的多个目的地消息的数量进行计数，以便提供多个广播消息类别计数。 然后基于广播消息类的广播消息类别计数来选择性地发送一类广播消息的多个目的地消息。

    Data management system and process
    80.
    发明授权
    Data management system and process 失效
    数据管理系统和流程

    公开(公告)号：US5878408A

    公开(公告)日：1999-03-02

    申请号：US761253

    申请日：1996-12-06

    申请人： Gary Alan Van Huben ,  Joseph Lawrence Mueller ,  Michael Steven Siegel ,  Thomas Bernard Warnock ,  Darryl James McDonald

    发明人： Gary Alan Van Huben ,  Joseph Lawrence Mueller ,  Michael Steven Siegel ,  Thomas Bernard Warnock ,  Darryl James McDonald

    IPC分类号： G06F17/50 ,  G06Q10/10 ,  G06F17/30

    CPC分类号： G06Q10/10 ,  G06F17/50 ,  G06F2217/04 ,  Y10S707/99931

    摘要： A design control system suitable for use in connection with the design of integrated circuits and other elements of manufacture having many parts which need to be developed in a concurrent engineering environment with inputs provided by users and or systems which may be located anywhere in the world provides a set of control information for coordinating movement of the design information through development and to release while providing dynamic tracking of the status of elements of the bills of materials in an integrated and coordinated activity control system utilizing a repository which can be implemented in the form of a database (relational, object oriented, etc.) or using a flat file system. Once a model is created and/or identified by control information design libraries hold the actual pieces of the design under control of the system without limit to the number of libraries, and providing for tracking and hierarchical designs which are allowed to traverse through multiple libraries. Data Managers become part of the design team, and libraries are programmable to meet the needs of the design group they service.

    摘要翻译： 适用于与集成电路设计有关的设计控制系统和具有许多部件的设计需要在具有由用户提供的输入和可能位于世界任何地方的系统的并行工程环境中开发的部件的设计控制系统中， 一组控制信息，用于通过开发和释放协调设计信息的移动，同时提供动态跟踪在综合和协调的活动控制系统中的物料清单的元素的状态，利用可以以 数据库（关系，面向对象等）或使用平面文件系统。 一旦通过控制信息设计库创建和/或识别了模型，就可以在系统的控制下保持设计的实际部分，而不限于库的数量，并提供允许遍历多个库的跟踪和分层设计。 数据管理器成为设计团队的一部分，库可编程，以满足他们服务的设计组的需求。