公开(公告)号：US20120313178A1

公开(公告)日：2012-12-13

申请号：US13158479

申请日：2011-06-13

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/3205 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US08198151B2

公开(公告)日：2012-06-12

申请号：US12890725

申请日：2010-09-27

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC: H01L21/8238

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

公开(公告)号：US08084824B2

公开(公告)日：2011-12-27

申请号：US12208352

申请日：2008-09-11

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L29/423

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 首先，提供具有第一晶体管区域和第二晶体管区域的衬底。 接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。 图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。 第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。

公开(公告)号：US07998818B2

公开(公告)日：2011-08-16

申请号：US12862799

申请日：2010-08-25

Applicant: Tian-Fu Chiang ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Tian-Fu Chiang ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.

Abstract translation: 提供一种形成半导体元件结构的方法。 首先，提供包括第一MOS和第二MOS的基板。 第一MOS的栅电极连接到第二MOS的栅电极，其中第一MOS包括第一高K材料和用于第一栅极的第一金属，第二MOS包括第二高K 材料和用于第二栅极的第二金属。 然后，第一栅极和第二栅极被部分地去除以形成连接凹部。 之后，用导电材料填充连接凹部，以形成用于电连接第一金属和第二金属的桥接通道。

公开(公告)号：US07888195B2

公开(公告)日：2011-02-15

申请号：US12198128

申请日：2008-08-26

Applicant: Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

Inventor： Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

IPC: H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S438/926

Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.

Abstract translation: 公开了一种用于制造具有金属栅极的晶体管的方法。 首先，提供衬底，其中衬底包括第一晶体管区域和第二晶体管区域。 在基板上形成多个虚拟栅极，在虚拟栅极上淀积介质层。 去除虚拟栅极以在电介质层中形成多个开口。 形成高k电介质层以覆盖电介质层和开口的表面，此后在高k电介质层上形成覆盖层。 去除设置在第二晶体管区域中的盖层，并且在第一晶体管区域的盖层和第二晶体管区域的高k电介质层上沉积金属层。 形成导电层以填充第一晶体管区域和第二晶体管区域的开口。

公开(公告)号：US07804141B2

公开(公告)日：2010-09-28

申请号：US12033017

申请日：2008-02-19

Applicant: Tian-Fu Chiang ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Tian-Fu Chiang ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L29/78

CPC classification number: H01L29/517 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.

Abstract translation: 半导体元件结构包括具有第一高K材料的第一MOS和用于第一栅极的第一金属，具有第二高K材料的第二MOS和用于第二栅极的第二金属和桥接通道 设置在连接第一栅极和第二栅极的凹部中，用于电连接第一栅极和第二栅极，其中桥接通道嵌入在第一栅极和第二栅极中的至少一个栅极中。

公开(公告)号：US20100155047A1

公开(公告)日：2010-06-24

申请号：US12338006

申请日：2008-12-18

Applicant: Chung-Hsiung Lin ,  Chien-Ting Lin

Inventor： Chung-Hsiung Lin ,  Chien-Ting Lin

IPC: G05D23/00 ,  F28F27/00

CPC classification number: H05K7/207 ,  G05D23/1932 ,  G06F1/206 ,  G06F2200/201 ,  H01L23/34 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a system to dissipate heat in an information handling system includes a first heat-generating component adapted to process first data and a second heat-generating component adapted to process second data. The system also includes a cooling fluid guide including an electroactive material. The cooling fluid guide is adapted to change from a first shape to a second shape, in response to receiving a trigger voltage or in response to no longer receiving the trigger voltage. The system also includes a controller adapted to detect a data load processed at the second heat-generating component and, in response to detecting the data load, to cause the trigger voltage to be received at, or no longer received at, the cooling fluid guide. The cooling fluid guide is adapted to direct an increased portion of cooling fluid toward the first heat-generating component when the cooling fluid guide is in a form of the second shape, as compared to the first shape.

Abstract translation: 在特定实施例中，在信息处理系统中散热的系统包括适于处理第一数据的第一发热组件和适于处理第二数据的第二发热组件。 该系统还包括包括电活性材料的冷却流体引导件。 响应于接收到触发电压或响应于不再接收到触发电压，冷却流体引导件适于从第一形状变化到第二形状。 该系统还包括控制器，适于检测在第二发热部件处理的数据负载，并且响应于检测到数据负载，使得触发电压在冷却流体导向件处接收或不再接收 。 与第一形状相比，当冷却流体引导件处于第二形状的形式时，冷却流体引导件适于将增加的冷却流体部分引向第一发热部件。

公开(公告)号：US07659189B2

公开(公告)日：2010-02-09

申请号：US11686961

申请日：2007-03-16

Applicant: Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

Inventor： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L29/518 ,  H01L21/28097 ,  H01L21/28229 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/78

Abstract: A semiconductor MOS device includes a semiconductor substrate; a gate oxide layer disposed on the semiconductor substrate; a fully silicided gate electrode disposed on the gate oxide layer; a composite thin film interposed between the fully silicided gate electrode and the gate oxide layer; a spacer on sidewall of the fully silicided gate electrode; and a source/drain region implanted into the semiconductor substrate next to the spacer. A method for forming the semiconductor MOS device is disclosed.

Abstract translation: 半导体MOS器件包括半导体衬底; 设置在所述半导体基板上的栅极氧化层; 设置在栅极氧化物层上的完全硅化的栅电极; 插入在完全硅化的栅极电极和栅极氧化物层之间的复合薄膜; 在全硅化物栅电极的侧壁上的间隔物; 以及注入到间隔物旁边的半导体衬底中的源极/漏极区域。 公开了一种用于形成半导体MOS器件的方法。

公开(公告)号：US20090258482A1

公开(公告)日：2009-10-15

申请号：US12101160

申请日：2008-04-11

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC: H01L21/283

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

公开(公告)号：US20090236669A1

公开(公告)日：2009-09-24

申请号：US12052728

申请日：2008-03-20

Applicant: Yi-Wen Chen ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Tian-Fu Chiang ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Yi-Wen Chen ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Tian-Fu Chiang ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/28079 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.

Abstract translation: 公开了一种用于制造金属栅极晶体管和多晶硅电阻器的方法。 首先，提供具有晶体管区域和电阻器区域的基板。 然后在衬底上形成多晶硅层以覆盖衬底的晶体管区域和电阻器区域。 接下来，去除设置在电阻器中的多晶硅层的一部分，并且对剩余的多晶硅层进行图案化以在布置在晶体管区域中的多晶硅层的表面和设置在电阻器中的多晶硅层的表面之间产生台阶高度 地区。