公开(公告)号：US06468812B2

公开(公告)日：2002-10-22

申请号：US09826231

申请日：2001-04-04

申请人： Dietrich Widmann ,  Georg Tempel

发明人： Dietrich Widmann ,  Georg Tempel

IPC分类号： H01L218239

CPC分类号： H01L27/11502 ,  H01L27/10852

摘要： A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor substrate, includes forming a trench in a layer applied to the substrate. An electrically conductive layer for the second capacitor electrode is deposited inside the trench and at least regionally conformally with side walls thereof. An auxiliary layer acting as a space-holder for the dielectric is conformally deposited inside the trench and on the electrically conductive layer for the second capacitor electrode. An electrically conductive layer for the first capacitor electrode is conformally deposited inside the trench and on the auxiliary layer. The auxiliary layer is at least partially removed to expose a hollow layer in at least a partial region between the two electrically conductive layers for the first and second capacitor electrodes. The dielectric is deposited into the exposed hollow layer between the two electrically conductive layers. A semiconductor memory device and a method for producing the device include producing the capacitor after production of the transistor and metallizing layers associated therewith for connection of the word and bit lines, in a configuration projecting upward from the plane; placing the capacitor in a trench formed inside a contact metallizing layer for the second electrode terminal of the transistor; and setting a depth of the trench to be equivalent to a layer thickness of the metallizing layer.

摘要翻译： 一种在形成于半导体衬底上的半导体电路器件中制造具有电介质和第一和第二电容器电极的电容器的方法，包括在施加到衬底的层中形成沟槽。 用于第二电容器电极的导电层沉积在沟槽内部并且至少在其侧壁上保持一致。 作为电介质的空间保持器的辅助层被共形沉积在沟槽内部和用于第二电容器电极的导电层上。 用于第一电容器电极的导电层共形沉积在沟槽内和辅助层上。 辅助层至少部分地被去除以暴露在用于第一和第二电容器电极的两个导电层之间的至少部分区域中的中空层。 电介质沉积在两个导电层之间的暴露的中空层中。 半导体存储器件及其制造方法包括在从晶体管向上突出的结构中制造晶体管和与之相关联的金属化层，用于连接字和位线的电容器; 将电容器放置在晶体管的第二电极端子的接触金属化层内形成的沟槽中; 并且将沟槽的深度设置为等于金属化层的层厚度。

公开(公告)号：US06232169B1

公开(公告)日：2001-05-15

申请号：US09200095

申请日：1998-11-25

申请人： Dietrich Widmann ,  Georg Tempel

发明人： Dietrich Widmann ,  Georg Tempel

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L27/10852

摘要： A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor substrate, includes forming a trench in a layer applied to the substrate. An electrically conductive layer for the second capacitor electrode is deposited inside the trench and at least regionally conformally with side walls thereof. An auxiliary layer acting as a space-holder for the dielectric is conformally deposited inside the trench and on the electrically conductive layer for the second capacitor electrode. An electrically conductive layer for the first capacitor electrode is conformally deposited inside the trench and on the auxiliary layer. The auxiliary layer is at least partially removed to expose a hollow layer in at least a partial region between the two electrically conductive layers for the first and second capacitor electrodes. The dielectric is deposited into the exposed hollow layer between the two electrically conductive layers. A semiconductor memory device and a method for producing the device include producing the capacitor after production of the transistor and metallizing layers associated therewith for connection of the word and bit lines, in a configuration projecting upward from the plane; placing the capacitor in a trench formed inside a contact metallizing layer for the second electrode terminal of the transistor; and setting a depth of the trench to be equivalent to a layer thickness of the metallizing layer.

摘要翻译： 一种在形成于半导体衬底上的半导体电路器件中制造具有电介质和第一和第二电容器电极的电容器的方法，包括在施加到衬底的层中形成沟槽。 用于第二电容器电极的导电层沉积在沟槽内部并且至少在其侧壁上保持一致。 作为电介质的空间保持器的辅助层被共形沉积在沟槽内部和用于第二电容器电极的导电层上。 用于第一电容器电极的导电层共形沉积在沟槽内和辅助层上。 辅助层至少部分地被去除以暴露在用于第一和第二电容器电极的两个导电层之间的至少部分区域中的中空层。 电介质沉积在两个导电层之间的暴露的中空层中。 半导体存储器件及其制造方法包括在从晶体管向上突出的结构中制造晶体管和与之相关联的金属化层，用于连接字和位线的电容器; 将电容器放置在晶体管的第二电极端子的接触金属化层内形成的沟槽中; 并且将沟槽的深度设置为等于金属化层的层厚度。

公开(公告)号：US6025626A

公开(公告)日：2000-02-15

申请号：US274500

申请日：1999-03-23

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L2924/0002

摘要： The invention relates to a self-adjusted nonvolatile memory cell, in which a MOS transistor with source and drain regions is incorporated into the surface region of a semiconductor body. The floating gate and the control gate of the MOS transistor are accommodated, overlapping one another, in a recess trench, while the transistor channel is guided laterally in a surface region of the trench.

摘要翻译： 本发明涉及一种自调整的非易失性存储单元，其中具有源区和漏区的MOS晶体管被结合到半导体本体的表面区域中。 MOS晶体管的浮置栅极和控制栅极彼此重叠地容纳在凹槽中，同时晶体管沟道在沟槽的表面区域被横向引导。

公开(公告)号：US5970338A

公开(公告)日：1999-10-19

申请号：US33139

申请日：1998-03-02

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8242

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： An EEPROM semiconductor structure is produced with a resistor, a thin-film transistor, a capacitor, and a transistor. The individual implantation steps are utilized to create various structures and, as a result, the production process is substantially simplified.

摘要翻译： 用电阻器，薄膜晶体管，电容器和晶体管制造EEPROM半导体结构。 单独的植入步骤用于产生各种结构，结果，生产过程被大大简化。

公开(公告)号：US5883832A

公开(公告)日：1999-03-16

申请号：US983290

申请日：1998-01-09

申请人： Georg Tempel ,  Josef Winnerl

发明人： Georg Tempel ,  Josef Winnerl

IPC分类号： G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7883 ,  H01L27/115

摘要： Electrically erasable and programmable non-volatile memory cell, which is formed with only one MOS transistor which is formed by a source-channel-drain junction, semi conductor substrate (1) of a first conductivity type has a drain region (2) and a source region (3) of a second conductivity type with a polarity opposite to that of the first conductivity type. A gate electrode (4), which is at a floating potential, is electrically insulated from the drain area (2) by a tunneling oxide (5) and from a channel region (9), which is located between the drain area and the source area (2, 3), by a gate oxide (5; 10). It and extends at least over a part of the channel region (9) and a part of the drain region (2) in the source-channel-drain direction. A control electrode (7) is electrically insulated from the gate electrode (4) by a coupling oxide (8).

摘要翻译： PCT No.PCT / DE96 / 01226 Sec。 371日期1998年1月9日 102（e）1998年1月9日PCT PCT 1996年7月8日PCT公布。 公开号WO97 / 04490 日期1997年2月6日由电子 - 沟道 - 漏极结形成的仅由一个MOS晶体管形成的电可擦除可编程非易失性存储单元具有第一导电类型的半导体衬底（1），漏极区域 （2）和具有极性与第一导电类型极性相反的第二导电类型的源极区（3）。 位于浮置电位的栅电极（4）通过隧道氧化物（5）与位于漏极区域和源极之间的沟道区域（9）与漏极区域（2）电绝缘， 区域（2,3），栅极氧化物（5; 10）。 并且在源极 - 漏极方向上延伸至沟道区域（9）的至少一部分和漏极区域（2）的一部分。 控制电极（7）通过耦合氧化物（8）与栅电极（4）电绝缘。

公开(公告)号：US5869860A

公开(公告)日：1999-02-09

申请号：US637163

申请日：1996-04-24

申请人： Dietrich Widmann ,  Georg Tempel

发明人： Dietrich Widmann ,  Georg Tempel

IPC分类号： H01L21/8247 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L27/10852

摘要： A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor substrate, includes forming a trench in a layer applied to the substrate. An electrically conductive layer for the second capacitor electrode is deposited inside the trench and at least regionally conformally with side walls thereof. An auxiliary layer acting as a space-holder for the dielectric is conformally deposited inside the trench and on the electrically conductive layer for the second capacitor electrode. An electrically conductive layer for the first capacitor electrode is conformally deposited inside the trench and on the auxiliary layer. The auxiliary layer is at least partial removed to expose a hollow layer in at least a partial region between the two electrically conductive layers for the first and second capacitor electrodes. The dielectric is deposited into the exposed hollow layer between the two electrically conductive layers. A semiconductor memory device and a method for producing the device include producing the capacitor after production of the transistor and metallizing layers associated therewith for connection of the word and bit lines, in a configuration projecting upward from the plane; placing the capacitor in a trench formed inside a contact metallizing layer for the second electrode terminal of the transistor; and setting a depth of the trench to be equivalent to a layer thickness of the metallizing layer.

摘要翻译： 一种在形成于半导体衬底上的半导体电路器件中制造具有电介质和第一和第二电容器电极的电容器的方法，包括在施加到衬底的层中形成沟槽。 用于第二电容器电极的导电层沉积在沟槽内部并且至少在其侧壁上保持一致。 作为电介质的空间保持器的辅助层被共形沉积在沟槽内部和用于第二电容器电极的导电层上。 用于第一电容器电极的导电层共形沉积在沟槽内和辅助层上。 辅助层至少部分去除以暴露出用于第一和第二电容器电极的两个导电层之间的至少部分区域中的中空层。 电介质沉积在两个导电层之间的暴露的中空层中。 半导体存储器件及其制造方法包括在从晶体管向上突出的结构中制造晶体管和与之相关联的金属化层，用于连接字和位线的电容器; 将电容器放置在晶体管的第二电极端子的接触金属化层内形成的沟槽中; 并且将沟槽的深度设置为等于金属化层的层厚度。