公开(公告)号：US08108643B2

公开(公告)日：2012-01-31

申请号：US11193184

申请日：2005-07-29

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G06F12/00

CPC分类号： G11C5/04 ,  G11C7/10

摘要： In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved. Each memory chip includes a rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a CAwD signal stream is to be sent to the own memory core and processed or re-driven to the next memory chip and whether a read data stream is to be taken from its own memory core or from a read data input interface to be re-driven to the next memory chip.

摘要翻译： 在具有环路向前架构的半导体存储器系统中，按照以下顺序将命令，地址和写入数据流以及以存储器芯片发送到基于协议的帧的形式的单独读取数据流：存储器控制器到第一存储器芯片 到第二存储器芯片到第三存储器芯片和第四存储器芯片，并且读取数据流从第四存储器芯片传送到存储器控制器。 对于每个命令，通常四个存储器芯片之一被访问用于数据处理，而四个存储器芯片中的三个只能实现CAwD流的简单重新驱动和读取数据流。 通过将未嵌入帧中的等级选择信号从存储器控制器分别传送到每个存储器芯片，可以实现对这些任务的更多灵活性。 每个存储器芯片包括等级选择切换部分，其接收单独传送的等级选择信号并从其中解码用于选择是否将CAwD信号流发送到自己的存储器核心并被处理或重新驱动到下一个存储器的信号状态 以及从其自己的存储器核心还是从读取的数据输入接口取出读取数据流以被重新驱动到下一个存储器芯片。

公开(公告)号：US07725647B2

公开(公告)日：2010-05-25

申请号：US11679732

申请日：2007-02-27

申请人： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

发明人： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0607

摘要： A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

摘要翻译： 存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。 存储器装置包括至少两个存储体。 每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。 至少两个数据分组处理设备被分配给不同的存储体存取设备。

公开(公告)号：US07325152B2

公开(公告)日：2008-01-29

申请号：US11170887

申请日：2005-06-30

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G06F1/04

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

摘要翻译： 提供了同步信号发生器，其包含第一和第二计数和延迟电路，它们都相对于复位信号同步/延迟电路处于分层位置。 复位信号同步/延迟电路和第一和第二计数和延迟电路由基本时钟信号或从其导出的第一时钟信号在频率和相位上相同，并且包含计数装置，其初始和最终计数状态是可调节的 为了以时钟方式设置由第一计数和延迟电路输出的第一和第二负载信号的时间位置以及由第二计数和延迟电路输出的FIFO读取时钟信号，以及 从而使它们适应包含同步信号发生器的半导体存储器系统的时间要求。

公开(公告)号：US07304909B2

公开(公告)日：2007-12-04

申请号：US11355801

申请日：2006-02-16

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222

摘要： A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input into it, and periodic control signals, that are likewise in sync with the basic clock, and to turn on/turn off output of at least the clock signal in reaction to an activation/deactivation signal, which is routed to it externally, to a synchronous parallel/serial converter executing synchronization and serialization of a parallel data signal with the basic clock. Whereas output of the clock signal and optionally of the control signals are turned off, immediately after the activation/deactivation signal has assumed its deactivation state, the control unit is able to synchronize turning control signals on again, when the activation/deactivation signal has assumed its activation state.

摘要翻译： 设置控制单元以产生和输出周期性的时钟信号，其与输入到其中的周期性基本时钟同步并且处于相同的频率，同时与基本时钟同步的周期性控制信号， 并且响应于从外部路由到其的激活/去激活信号，至少打开/关闭至少时钟信号的输出到执行与基本时钟的并行数据信号的同步和串行化的同步并行/串行转换器 。 尽管时钟信号的输出和可选择的控制信号的输出在激活/去激活信号已经采取其去激活状态之后立即关闭，但是当激活/去激活信号已经假定时，控制单元能够再次同步转向控制信号 其激活状态。

公开(公告)号：US20070247929A1

公开(公告)日：2007-10-25

申请号：US11735928

申请日：2007-04-16

申请人： Paul Wallner ,  Stefan Dietrich ,  Peter Gregorius

发明人： Paul Wallner ,  Stefan Dietrich ,  Peter Gregorius

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

摘要翻译： 一种存储器件，包括存储单元阵列; 用于接收命令数据并向存储单元阵列提供驱动信号的输入电路; 用于缓冲从存储单元阵列读出的数据的输出缓冲器; 以及用于驱动输出缓冲器的定时器，使得在经过预定时间间隔之后的输出处提供缓冲数据，从提供驱动信号开始的预定时间间隔。

公开(公告)号：US20070201296A1

公开(公告)日：2007-08-30

申请号：US11679732

申请日：2007-02-27

申请人： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

发明人： Paul Wallner ,  Tim Schoenauer ,  Peter Gregorius ,  Daniel Kehrer

IPC分类号： G11C8/00

CPC分类号： G06F12/0607

摘要： A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.

摘要翻译： 存储器装置包括被配置为根据预定义的协议以数据分组的形式发送数据的接口。 存储器装置包括至少两个存储体。 每个存储体包括至少一个存储单元。 存储器装置包括至少两个存储体存取装置，其配置成便于访问至少两个存储体中的每一个的至少一个存储单元的数据。 该存储器装置包括被配置为对数据包进行编码和/或解码的至少两个数据包处理装置。 至少两个数据分组处理设备被分配给不同的存储体存取设备。

公开(公告)号：US07245239B2

公开(公告)日：2007-07-17

申请号：US11331478

申请日：2006-01-13

申请人： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

发明人： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/107

摘要： A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

摘要翻译： 公开了一种同步并行/串行转换器。 在一个实施例中，一个同步并行/串行转换器，其接收并行n位输入信号并且包括第一移位寄存器，该第一移位寄存器与具有第一移位寄存器的时钟信号同步地接收具有第一加载信号的输入信号的奇数部分 时钟速率是系统时钟的一半时钟速率，并提供串行输出作为第一个一位信号序列; 第二移位寄存器，其以与所述时钟信号同步的第二负载信号接收所述输入信号的偶数部分，并提供串行输出作为第二一比特信号序列; 以及融合单元，其与时钟信号和第二串行1位信号序列同步地与时钟信号同步地熔接第一串行1位信号序列，以形成串行一位输出信号。

公开(公告)号：US20070006057A1

公开(公告)日：2007-01-04

申请号：US11171585

申请日：2005-06-30

申请人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

IPC分类号： G11C29/00

CPC分类号： G11C7/1006

摘要： Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according to the respective signal type and scheduling the memory core and sections of the interface circuit respectively for the decoded signal. The interface circuit further comprises a CRC bit decoding and check unit and a protection circuit arranged for protecting the memory core and for enabling/disabling switching through of signal transfer from the interface circuit to the memory core depending on a correct/incorrect signal generated by the CRC bit decoding and check unit according to the result of checking an information within the frame by means of the CRC bits which are inserted in a signal frame in association to the respective information in accordance with a defined transmission protocol.

摘要翻译： 提供了一种半导体存储器芯片，其包括存储器核心和具有解码，选择和调度电路装置的接口电路，用于从信号帧解码相应类型的数据信号，命令信号和地址信号，选择所需的动作 存储器芯片，分别对接收电路的存储器核心部分和解码信号进行调度。 接口电路还包括CRC位解码和校验单元以及保护电路，该保护电路用于保护存储器核心并根据由该接口电路产生的正确/不正确的信号来允许/禁止从接口电路到存储器核心的信号传输切换 CRC比特解码和校验单元根据通过根据定义的传输协议与插入到信号帧中的各个信息相关联的CRC比特来检查帧内的信息的结果。

公开(公告)号：US20060181444A1

公开(公告)日：2006-08-17

申请号：US11331478

申请日：2006-01-13

申请人： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

发明人： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/107

摘要： A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

摘要翻译： 公开了一种同步并行/串行转换器。 在一个实施例中，一个同步并行/串行转换器，其接收并行n位输入信号并且包括第一移位寄存器，该第一移位寄存器与具有第一移位寄存器的时钟信号同步地接收具有第一加载信号的输入信号的奇数部分 时钟速率是系统时钟的一半时钟速率，并提供串行输出作为第一个一位信号序列; 第二移位寄存器，其以与所述时钟信号同步的第二负载信号接收所述输入信号的偶数部分，并提供串行输出作为第二一比特信号序列; 以及融合单元，其与时钟信号和第二串行1位信号序列同步地与时钟信号同步地熔接第一串行1位信号序列，以形成串行一位输出信号。

公开(公告)号：US08305834B2

公开(公告)日：2012-11-06

申请号：US12710800

申请日：2010-02-23

申请人： Michael Richter ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Thomas Hein ,  Andreas Schneider

发明人： Michael Richter ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Thomas Hein ,  Andreas Schneider

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087

摘要： A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.

摘要翻译： 一种半导体存储器，包括设置在集成电路上的多个存储体，每个存储体包括存储单元阵列，其中多个存储体的存储单元的第一部分具有第一存取速度和第二部分存储单元 多个存储器组具有第二存取速度，其中第一存取速度与第二存取速度不同。