公开(公告)号：US07587655B2

公开(公告)日：2009-09-08

申请号：US11259376

申请日：2005-10-26

申请人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

IPC分类号： G11C29/00

CPC分类号： G11C8/18

摘要： Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

摘要翻译： 用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。 数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。 附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。

公开(公告)号：US20080222443A1

公开(公告)日：2008-09-11

申请号：US11813952

申请日：2006-01-04

申请人： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

发明人： Paul Wallner ,  Peter Gregorius ,  Ralf Schledz

IPC分类号： G06F1/08

CPC分类号： H03M9/00

摘要： The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).

摘要翻译： 本发明涉及一种与时钟信号（clk_hr_i）同步控制的与设备（1）输入的连续时钟信号（clk_hr_i）同步的控制信号（evload_o，odload_o，st_chgclk_o，clk_o，st_chgclk_o，clk_o，stkorfiford_i） ，其中所述控制器（SE）具有：寄存器装置，用于登记包括多个位位置的至少一个设置信号（st_load_i，st_fiford_i），用于根据一个或多个位位置对时钟信号（clk_hr_i）的边沿进行计数的计数装置 设置分别登记在寄存器装置中的信号，以及同步和输出装置，用于使由计数装置计数的值与时钟信号（clk_hr_i）和登记的设置信号同步，并输出至少一个控制信号，其中寄存器装置， 计数装置和同步和输出装置被配置和彼此连接，使得输出控制信号取决于相应的 有效登记的设定信号占据（占据）多个时间位置中的一个，具有与时钟信号的前沿或后沿同步的半个时钟周期的整数倍的相位差。 控制器可以特别用于控制同步并行 - 串行转换器，用于将包括k位位置的并行输入信号转换为与时钟信号（clk_hr_i）同步的串行输出信号序列，该时钟信号（clk_hr_i）被提供在发送电路中 接口电路的即将到来的存储器生成（例如DDR4）的非常快的DDR DRAM半导体存储器组件。

公开(公告)号：US07221615B2

公开(公告)日：2007-05-22

申请号：US11242150

申请日：2005-10-04

申请人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

发明人： Paul Wallner ,  Martin Streibl ,  Manfred Menke ,  Yukio Fukuzo ,  Christian Sichert ,  Peter Gregorius

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C11/4096

摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。

公开(公告)号：US07173877B2

公开(公告)日：2007-02-06

申请号：US10955177

申请日：2004-09-30

申请人： Hermann Ruckerbauer ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G11C8/00

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

摘要翻译： 本发明涉及一种具有两条时钟线的存储器件的存储器系统。 本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控​​制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线 向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回 到存储器控制器的读时钟输入。 存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

公开(公告)号：US20070028028A1

公开(公告)日：2007-02-01

申请号：US11193184

申请日：2005-07-29

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G11C5/04 ,  G11C7/10

摘要： In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved. Each memory chip includes a rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a CAwD signal stream is to be sent to the own memory core and processed or re-driven to the next memory chip and whether a read data stream is to be taken from its own memory core or from a read data input interface to be re-driven to the next memory chip.

摘要翻译： 在具有环路向前架构的半导体存储器系统中，按照以下顺序将命令，地址和写入数据流以及以存储器芯片发送到基于协议的帧的形式的单独读取数据流：存储器控制器到第一存储器芯片 到第二存储器芯片到第三存储器芯片和第四存储器芯片，并且读取数据流从第四存储器芯片传送到存储器控制器。 对于每个命令，通常访问四个存储器芯片中的一个用于数据处理，而四个存储器芯片中的三个只能实现CAwD流的简单重新驱动并读取数据流流。 通过将未嵌入帧中的等级选择信号从存储器控制器分别传送到每个存储器芯片，可以实现对这些任务的更多灵活性。 每个存储器芯片包括等级选择切换部分，其接收单独传送的等级选择信号并从其中解码用于选择是否将CAwD信号流发送到自己的存储器核心并被处理或重新驱动到下一个存储器的信号状态 以及从其自己的存储器核心还是从读取的数据输入接口取出读取数据流以被重新驱动到下一个存储器芯片。

公开(公告)号：US20060285424A1

公开(公告)日：2006-12-21

申请号：US11152769

申请日：2005-06-15

申请人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Paul Wallner ,  Thomas Rickes

IPC分类号： G11C8/00

CPC分类号： G06F13/4243 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/107

摘要： A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized read data stream to a serial read data input terminal of a corresponding second interface circuit section of a succeeding same memory chip or to a memory controller.

摘要翻译： 在包括存储器核心，第一接口电路部分和第二接口电路部分的半导体存储器芯片中实现高速接口电路。 第一接口电路部分可连接到写数据/命令和地址信号总线，包括写数据/命令和地址重新驱动器/发射机路径（其可以是透明的）并且不包括任何时钟信号同步电路， 以及包括串行到并行转换和同步装置的主写信号路径，以与接收到的写数据/命令和地址信号的参考时钟信号同步并将并行转换的写入信号传送到存储器核。 第二接口电路部分可连接到读数据总线，并且包括用于将接收的串行读取数据发送和重新驱动到后续半导体存储器芯片的透明读取数据重新驱动器/发送器路径和用于插入并行的主读取信号路径 将串行转换的读取数据从存储器核心转换成接收到的串行读取数据流，将并行到串行转换的读取数据与参考时钟信号同步，并将串行读取数据流提供给串行读取数据输入端 相应的相同存储器芯片的相应的第二接口电路部分或存储器控制器。

公开(公告)号：US20060221761A1

公开(公告)日：2006-10-05

申请号：US11355801

申请日：2006-02-16

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222

摘要： A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input into it, and periodic control signals, that are likewise in sync with the basic clock, and to turn on/turn off output of at least the clock signal in reaction to an activation/deactivation signal, which is routed to it externally, to a synchronous parallel/serial converter executing synchronization and serialization of a parallel data signal with the basic clock. Whereas output of the clock signal and optionally of the control signals are turned off, immediately after the activation/deactivation signal has assumed its deactivation state, the control unit is able to synchronize turning control signals on again, when the activation/deactivation signal has assumed its activation state.

摘要翻译： 设置控制单元以产生和输出周期性的时钟信号，其与输入到其中的周期性基本时钟同步并且处于相同的频率，同时与基本时钟同步的周期性控制信号， 并且响应于从外部路由到其的激活/去激活信号，至少打开/关闭至少时钟信号的输出到执行与基本时钟的并行数据信号的同步和串行化的同步并行/串行转换器 。 尽管时钟信号的输出和可选择的控制信号的输出在激活/去激活信号已经采取其去激活状态之后立即关闭，但是当激活/去激活信号已经假定时，控制单元能够再次同步转向控制信号 其激活状态。

公开(公告)号：US07050340B1

公开(公告)日：2006-05-23

申请号：US10986767

申请日：2004-11-15

申请人： Hermann Ruckerbauer ,  Dominique Savignac ,  Christian Sichert ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Dominique Savignac ,  Christian Sichert ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/1018

摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.

摘要翻译： 用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串 具体的突发长度。 该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

公开(公告)号：US07334150B2

公开(公告)日：2008-02-19

申请号：US11002148

申请日：2004-12-03

申请人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G06F1/04

CPC分类号： G11C5/04 ,  G11C5/063

摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

公开(公告)号：US20070047372A1

公开(公告)日：2007-03-01

申请号：US11509092

申请日：2006-08-24

申请人： Paul Wallner ,  Andre Schafer ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schafer ,  Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C7/1051 ,  G11C2207/107

摘要： A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

摘要翻译： 半导体存储器系统包括半导体存储器芯片，其中数据，命令和地址信号在与预定协议相对应的信号帧中的存储器控​​制器和半导体存储器芯片之间串行发送。 在半导体存储器芯片内的接收信号路径中，用于对信号帧进行解码的帧解码器被布置在接收接口设备之后，并且在帧解码器和存储器核心之间，布置中间存储设备，其具有包括单元阵列 多个存储器单元，以及寻址和选择器电路，由帧解码器从由存储器控制器提供的命令和/或写入信号帧解码的地址信号被应用于寻址单元阵列并用于选择要写入的写入数据 进入单元阵列并从单元阵列中读出。