公开(公告)号：US5646436A

公开(公告)日：1997-07-08

申请号：US536934

申请日：1995-09-29

申请人： Gary Hong ,  Chen-Chiu Hsue ,  Chen-Hui Chung

发明人： Gary Hong ,  Chen-Chiu Hsue ,  Chen-Hui Chung

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/265

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A Read-Only Memory (ROM) device produced by self-aligned implantation. First, a non-coded mask ROM with a silicon substrate, a plurality of bit-lines formed in the substrate, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together form arrays of memory cells, is provided. Next, an aligning layer is formed above the word-lines. A photoresist is thereafter coated on the surface of the aligning layer. Then, portions of the photoresist not covered by a mask pattern are etched away to the aligning layer so as to provide openings exposing portions of the memory cells that will be programmed to operate in a first conduction state. Portions of the aligning layer exposed through the openings are then removed, after which impurities are implanted through the openings and into the substrate to enable the memory cells that are to operate in the first conduction state, and leave other non-programmed memory cells operating in a second conduction state.

摘要翻译： 通过自对准植入制造的只读存储器（ROM）器件。 首先，具有硅衬底的非编码掩模ROM，在衬底中形成的多个位线，形成在位线上的栅极氧化层，以及形成在栅极氧化物上的多个字线，其一起 提供了存储单元的阵列。 接下来，在字线上形成对准层。 然后将光致抗蚀剂涂覆在对准层的表面上。 然后，未被掩模图案覆盖的部分光致抗蚀剂被蚀刻掉到对准层上，以便提供露出将被编程为在第一导通状态下操作的存储单元部分的开口。 然后去除通过开口暴露的对准层的部分，之后通过开口注入杂质并进入衬底，以使得能够在第一导通状态下操作的存储器单元，并且使其他非编程存储器单元在 第二导通状态。

公开(公告)号：US5635749A

公开(公告)日：1997-06-03

申请号：US537138

申请日：1995-09-29

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/1045

摘要： A MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.

摘要翻译： MOSFET晶体管器件，其栅极形成在具有栅极的轻掺杂半导体衬底上，以及源极区和漏极区。 将VT1离子均匀地注入基片的表面，形成具有基本均匀掺杂的VT区域，该VT区域在其表面附近的衬底上部。 在衬底上形成栅氧化层。 栅极导体沉积在栅极氧化物层上。 在源区域上的器件区域中注入大角度植入物。 然后注入离子以形成与栅极自对准的源区和漏区。

公开(公告)号：US5596230A

公开(公告)日：1997-01-21

申请号：US583197

申请日：1996-01-04

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L21/76801 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A device and a method of formation on a substrate of a semiconductor interconnection via structure for semiconductor devices is provided. Initially, form a first metal layer on the substrate, a first dielectric layer upon the first metal layer, and a mask upon the dielectric layer with a metal etching pattern therein. Then, etch through the first dielectric layer and the first metal layer to the substrate forming trenches between metal lines formed from the first metal layer covered with the dielectric layer. Next, form a first etch stop layer upon the surface of the the first dielectric layer and planarize it, a second dielectric layer above the etch stop layer, and a second etch stop layer on the second dielectric layer. Then, pattern the second dielectric and the second etch stop layer and etch to form a via hole down to a surface of the first metal layer. Then, form a second metal layer and a metal plug in the via hole extending into contact with the first metal layer.

摘要翻译： 提供了一种用于半导体器件的半导体互连通孔结构的衬底上的器件和方法。 首先，在基板上形成第一金属层，在第一金属层上形成第一介电层，在介质层上形成具有金属蚀刻图案的掩模。 然后，通过第一介电层和第一金属层蚀刻到由覆盖有电介质层的第一金属层形成的金属线之间形成沟槽的衬底。 接下来，在第一介电层的表面上形成第一蚀刻停止层并使其平坦化，在蚀刻停止层上方的第二介电层和第二介电层上的第二蚀刻停止层。 然后，对第二电介质和第二蚀刻停止层进行图案化并蚀刻以形成到第一金属层的表面的通孔。 然后，在通孔中形成与第一金属层接触的第二金属层和金属塞。

公开(公告)号：US5576228A

公开(公告)日：1996-11-19

申请号：US446225

申请日：1995-05-22

申请人： Ancheor Chen ,  Gary Hong

发明人： Ancheor Chen ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/6656

摘要： A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.

公开(公告)号：US5556798A

公开(公告)日：1996-09-17

申请号：US347715

申请日：1994-12-01

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/762 ,  H01L21/8247 ,  A01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/762

摘要： A method of fabricating semiconductor integrated circuit non-volatile memory devices having memory cell isolation between the memory cells without increasing device dimension. Active regions are defined by forming field oxide layers on a on semiconductor substrate of a first type. Lightly-doped regions of the first type are formed underneath field oxide layers. Additional heavily-doped regions of the first type are formed within each of the lightly-doped regions. Active regions on the semiconductor substrate are implanted with impurities of a second type to form drains and sources for the memory cells. Floating gate layers are formed on tunnel oxide layers, the tunnel oxide layers separating the floating gate layers from the active regions. The presence of the lightly-doped region improves the breakdown voltage, while the additional heavily-doped regions within each of the lightly-doped regions increases threshold and punchthrough voltages for the inherent parasitic transistors of the memory device.

摘要翻译： 一种在不增加器件尺寸的情况下制造在存储器单元之间具有存储单元隔离的半导体集成电路非易失性存储器件的方法。 通过在第一类型的半导体衬底上形成场氧化物层来限定有源区。 第一类型的轻掺杂区域形成在场氧化物层下面。 在每个轻掺杂区域内形成第一类型的附加重掺杂区域。 在半导体衬底上的有源区域注入第二类型的杂质以形成存储器单元的漏极和源极。 浮动栅极层形成在隧道氧化物层上，隧道氧化物层将浮动栅极层与活性区域分开。 轻掺杂区域的存在改善了击穿电压，而每个轻掺杂区域内的附加重掺杂区域增加了存储器件固有寄生晶体管的阈值和穿透电压。

公开(公告)号：US5554551A

公开(公告)日：1996-09-10

申请号：US344005

申请日：1994-11-23

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247

CPC分类号： H01L27/11517 ,  Y10S438/981

摘要： An EEPROM cell is made by forming a first dielectric layer on a substrate, forming a tunnel mask with an tunnel opening used for etching the dielectric layer to form a tunnel window, doping a region of the substrate through the tunnel window and stripping the tunnel mask. A spacer frame is made about the perithery of the window over the first doped region of the substrate. A second dielectric layer is formed over the first doped region within the spacer frame which is then removed. Tunnel oxide is deposited on the exposed surface of the first doped region, a floating gate layer is deposited, mask and etched. The mask is stripped Ions are implanted into buried N+ source/drain regions through exposed surfaces of the gate oxide near the floating gate. A blanket interconductor layer covers the device. A control gate layer is deposited, mask and etched. The control gate mask is then removed.

摘要翻译： 通过在衬底上形成第一电介质层，形成具有用于蚀刻电介质层的隧道开口的隧道掩模以形成隧道窗口，通过隧道窗口掺杂衬底的区域并剥离隧道掩模来制造EEPROM单元 。 围绕衬底的第一掺杂区域上的窗口的外面形成间隔框架。 第二介电层形成在间隔框架内的第一掺杂区域上，然后将其去除。 隧道氧化物沉积在第一掺杂区域的暴露表面上，沉积浮栅，掩模和蚀刻。 掩模被剥离通过浮栅附近的栅极氧化物的暴露表面将离子注入掩埋的N +源极/漏极区。 毯子互导层覆盖该设备。 控制栅极层被沉积，掩模和蚀刻。 然后移除控制门掩模。

公开(公告)号：US5512770A

公开(公告)日：1996-04-30

申请号：US427213

申请日：1995-04-24

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288

CPC分类号： H01L29/66553 ,  H01L21/823412 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/66537 ,  H01L29/66545

摘要： This invention describes a device structure and a method of forming the device structure using a polysilicon spacer formed on the edges of the gate electrode forming a gate structure with a cavity. The channel area is self aligned through this cavity. A fully overlapped Lightly-Doped-Drain structure is used to improve device characteristics for submicron devices. A deep boron implant region, self aligned through the gate structure, is used to improve punch through voltage.

摘要翻译： 本发明描述了使用形成在具有空腔的栅极结构的栅电极的边缘上形成的多晶硅间隔来形成器件结构的器件结构和方法。 通道区域通过该腔体自对准。 完全重叠的轻掺杂结构用于提高亚微米器件的器件特性。 通过栅极结构自对准的深硼注入区域用于提高穿通电压。

公开(公告)号：US5496747A

公开(公告)日：1996-03-05

申请号：US100422

申请日：1993-08-02

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A split-gate memory cell and its fabrication are described. The semiconductor substrate is of a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate comprises a first layer of conductive material, a second layer of dielectric material, and a third layer also composed of a second conductive layer. First and second sidewall dielectric spacers are formed adjacent to the first edge and the second opposing edge, respectively of the gate. Ions are implanted into the substrate. Those ions comprise a species of an opposite conductivity type. The ions are implanted at a substantial acute angle relative to a vertical angle with respect to the substrate. A third conductive material is deposited upon the second conductive layer and the first and second sidewall dielectric spacers. The third conductive material is in electrical contact with the second conductive layer.

摘要翻译： 描述了分闸存储器单元及其制造。 半导体衬底是第一导电类型。 该过程开始于形成覆盖衬底的导电栅极，但是通过第一电介质材料层与其电绝缘。 栅极包括导电材料的第一层，第二介电材料层，以及也由第二导电层构成的第三层。 分别与栅极的第一边缘和第二相对边缘相邻地形成第一和第二侧壁电介质间隔物。 离子植入衬底。 这些离子包括相反导电类型的物质。 离子相对于衬底相对于垂直角以大的锐角植入。 第三导电材料沉积在第二导电层和第一和第二侧壁电介质间隔物上。 第三导电材料与第二导电层电接触。

公开(公告)号：US5494839A

公开(公告)日：1996-02-27

申请号：US237352

申请日：1994-05-03

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/027 ,  H01L21/3213 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/0274 ,  H01L21/32139 ,  Y10S438/943

摘要： A dual photo-resist process for fabricating capacitor plates of a DRAM is disclosed including the step of forming a capacitor on a semiconductor IC surface. A first plurality of photo-resist regions which are separated from each other by spaces are then formed on the capacitor plate layer. At least one second photo-resist region is then formed on the capacitor plate layer which partially fills a space between, and is adjacent to one of, two of the first photo-resist regions. The capacitor plate layer is then etched below the spaces between the first and second photo-resist regions to form a plurality of individual capacitor plates including one capacitor plate for each DRAM cell.

摘要翻译： 公开了一种用于制造DRAM的电容器板的双光阻工艺，包括在半导体IC表面上形成电容器的步骤。 然后在电容器板层上形成通过间隔彼此分开的第一多个光致抗蚀剂区域。 然后在电容器板层上形成至少一个第二光刻抗蚀剂区域，其部分地填充两个第一光致抗蚀剂区域之间的空间，并且邻近其中之一。 然后在第一和第二光致抗蚀剂区域之间的空间下方蚀刻电容器板层，以形成多个单独的电容器板，其包括用于每个DRAM单元的一个电容器板。

公开(公告)号：US5482879A

公开(公告)日：1996-01-09

申请号：US439917

申请日：1995-05-12

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A process of fabricating a split gate flash memory cell first forms a stacked-gate structure on a face of a substrate. The stacked-gate structure includes a tunnel oxide, a polysilicon floating gate, an inter-poly dielectric and a first polysilicon control gate. A drain region is formed into the substrate at one side of the stacked-gate structure, and is self-aligned with the stacked-gate structure. Thermal oxidation is performed to form sidewall oxides on the sidewalls of the stacked-gate structure, and gate oxide on the substrate. A second polysilicon control gate is deposited over the first polysilicon control gate, sidewall oxides and gate oxide, and is connected with the first polysilicon control gate to form a common control gate. A source region is formed in the substrate at another side of the stacked-gate structure, and is self-aligned with the substantially upright portion of the second polysilicon control gate located at the another side of the stacked-gate structure.

摘要翻译： 首先制造分离栅闪存单元的工艺首先在基板的表面上形成堆叠栅极结构。 堆叠栅极结构包括隧道氧化物，多晶硅浮动栅极，多晶硅电介质和第一多晶硅控制栅极。 在层叠栅极结构的一侧形成漏极区，并与层叠栅结构自对准。 进行热氧化以在堆叠栅极结构的侧壁上形成侧壁氧化物，并在基板上形成栅极氧化物。 第二多晶硅控制栅极沉积在第一多晶硅控制栅极，侧壁氧化物和栅极氧化物上，并且与第一多晶硅控制栅极连接以形成公共控制栅极。 源极区域形成在层叠栅极结构的另一侧的衬底中，并且与位于堆叠栅极结构的另一侧的第二多晶硅控制栅极的基本上直立的部分自对准。