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    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING
    72.
    发明申请
    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING 审中-公开

    公开(公告)号：US20180173675A1

    公开(公告)日：2018-06-21

    申请号：US15386919

    申请日：2016-12-21

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F15/80

    CPC classification number: G06F15/80 ,  G06F8/47 ,  G06F9/44547

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING
    73.
    发明申请
    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING 审中-公开

    公开(公告)号：US20180173529A1

    公开(公告)日：2018-06-21

    申请号：US15386990

    申请日：2016-12-21

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F9/30 ,  G06F9/48

    CPC classification number: G06F9/485 ,  G06F8/41 ,  G06F9/3009 ,  G06F9/4856 ,  G06F9/5088 ,  Y02D10/24 ,  Y02D10/32

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

    Shared buffers for processing elements on a network device
    74.
    发明授权
    Shared buffers for processing elements on a network device 有权

    公开(公告)号：US09973335B2

    公开(公告)日：2018-05-15

    申请号：US13839080

    申请日：2013-03-15

    Applicant: INTEL CORPORATION

    Inventor： Ben-Zion Friedman ,  Eliezer Tamir ,  Eliel Louzoun ,  Ohad Falik

    IPC: H04L9/06 ,  G06F21/72 ,  H04L29/06

    CPC classification number: H04L9/0618 ,  G06F21/72 ,  H04L63/0485

    Abstract: Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.

    Socket management with reduced latency packet processing
    75.
    发明授权
    Socket management with reduced latency packet processing 有权
    Socket管理采用减少延迟的数据包处理

    公开(公告)号：US09558132B2

    公开(公告)日：2017-01-31

    申请号：US13966761

    申请日：2013-08-14

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Eliel Louzoun ,  Matthew R. Wilcox

    IPC: H04L12/28 ,  G06F13/00

    CPC classification number: H04L47/56 ,  G06F13/00 ,  G06F13/24 ,  G06F13/28 ,  G06F13/385

    Abstract: Generally, this disclosure provides systems, methods and computer readable media for management of sockets and device queues for reduced latency packet processing. The method may include maintaining a unique-list comprising entries identifying device queues and an associated unique socket for each of the device queues, the unique socket selected from a plurality of sockets configured to receive packets; busy-polling the device queues on the unique-list; receiving a packet from one of the plurality of sockets; and updating the unique-list in response to detecting that the received packet was provided by an interrupt processing module. The updating may include identifying a device queue associated with the received packet; identifying a socket associated with the received packet; and if the identified device queue is not on one of the entries on the unique-list, creating a new entry on the unique-list, the new entry comprising the identified device queue and the identified socket.

    Abstract translation: 通常，本公开提供了用于管理套接字和设备队列以用于减少等待时间分组处理的系统，方法和计算机可读介质。 该方法可以包括维护包括标识设备队列的条目的唯一列表和用于每个设备队列的相关联的唯一套接字，所述唯一套接字从被配置为接收分组的多个套接字中选择; 在唯一列表上轮询设备队列; 从所述多个插座中的一个接收数据包; 以及响应于检测到所接收的分组是由中断处理模块提供的，更新所述唯一列表。 所述更新可以包括识别与所接收的分组相关联的设备队列; 识别与所接收的分组相关联的套接字; 并且如果所识别的设备队列不在唯一列表上的条目之一上，则在唯一列表上创建新条目，新条目包括所识别的设备队列和所识别的套接字。

    Facilitating, at least in part, by circuitry, accessing of at least one controller command interface
    77.
    发明授权
    Facilitating, at least in part, by circuitry, accessing of at least one controller command interface 有权
    至少部分地通过电路，至少访问一个控制器命令界面

    公开(公告)号：US08996755B2

    公开(公告)日：2015-03-31

    申请号：US14162468

    申请日：2014-01-23

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Theodore L. Willke ,  Eliel Louzoun ,  Matthew R. Wilcox ,  Donald E. Wood ,  Steven B. McGowan ,  Robert O. Sharp

    IPC: G06F3/00 ,  G06F15/167 ,  G06F13/38

    CPC classification number: G06F15/17331 ,  G06F13/385 ,  G06F15/167 ,  H04L67/1097

    Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.

    Abstract translation: 一个实施例可以包括至少部分地促进客户端中的第一网络接口控制器（NIC）的电路，以便能够通过远离客户端的服务器中的第二NIC以独立的方式访问 的服务器中的操作系统环境，服务器的另一个控制器的至少一个命令接口。 命令接口可以包括至少一个控制器命令队列。 这种访问可以包括将至少一个队列元素写入至少一个命令队列以命令另一控制器执行与另一个控制器相关联的至少一个操作。 另一个控制器可以至少部分地响应于至少一个队列元素来执行至少一个操作。 许多替代方案，变化和修改是可能的。

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