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    Scalable techniques for data transfer between virtual machines
    3.
    发明授权
    Scalable techniques for data transfer between virtual machines 有权

    公开(公告)号：US11494220B2

    公开(公告)日：2022-11-08

    申请号：US16810400

    申请日：2020-03-05

    Applicant: INTEL CORPORATION

    Inventor： Ben-Zion Friedman ,  Eliezer Tamir

    IPC: G06F21/00 ,  G06F9/455 ,  G06F9/54 ,  G06F21/60 ,  G06F21/53

    Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. In an example embodiment, an apparatus may include circuitry and memory storing instructions for execution by the circuitry to assign each one of a plurality of shared virtual memory spaces to a respective one of a plurality of virtual machines, wherein a first shared virtual memory space of the plurality of shared virtual memory spaces is assigned to a first virtual machine of the plurality of virtual machines, write, by the first virtual machine to the first shared virtual memory space, data to be provided to a second virtual machine of the plurality of virtual machines, and read, by the second virtual machine, the data in the first shared virtual memory space.

    Computing devices and server systems with processing cores having different instruction set architectures
    5.
    发明授权
    Computing devices and server systems with processing cores having different instruction set architectures 有权

    公开(公告)号：US10684984B2

    公开(公告)日：2020-06-16

    申请号：US15386833

    申请日：2016-12-21

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F15/80 ,  G06F9/455 ,  G06F8/76

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    6.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    Applicant: Intel Corporation

    Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC: G06F1/32

    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

    Unified device interface for a multi-bus system
    7.
    发明授权
    Unified device interface for a multi-bus system 有权

    公开(公告)号：US09703742B2

    公开(公告)日：2017-07-11

    申请号：US14498165

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Eliel Louzoun

    IPC: G06F3/00 ,  G06F13/36 ,  G06F13/40 ,  G06F9/50 ,  G06F13/24

    CPC classification number: G06F13/4072 ,  G06F9/5083 ,  G06F13/24 ,  G06F13/4022

    Abstract: The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances.

    Techniques for forwarding or receiving data segments associated with a large data packet
    8.
    发明授权
    Techniques for forwarding or receiving data segments associated with a large data packet 有权

    公开(公告)号：US09686190B2

    公开(公告)日：2017-06-20

    申请号：US13839393

    申请日：2013-03-15

    Applicant: INTEL CORPORATION

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: H04L12/721 ,  H04L12/805

    CPC classification number: H04L45/72 ,  H04L47/36

    Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.

    Techniques for remote client access to a storage medium coupled with a server
    9.
    发明授权
    Techniques for remote client access to a storage medium coupled with a server 有权
    用于远程客户端访问与服务器耦合的存储介质的技术

    公开(公告)号：US09467512B2

    公开(公告)日：2016-10-11

    申请号：US13743170

    申请日：2013-01-16

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Phil C. Cayton ,  Theodore L. Willke ,  Frank Berry

    IPC: G06F13/12 ,  G06F15/167 ,  H04L29/08 ,  G06F21/80 ,  G06F21/44 ,  G06F21/79 ,  H04L29/06 ,  G06F3/06

    CPC classification number: G06F15/17331 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688 ,  G06F13/4282 ,  G06F15/167 ,  G06F21/44 ,  G06F21/79 ,  G06F21/80 ,  G06F2213/0026 ,  H04L67/1097 ,  H04L69/12 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Examples include client access to a storage medium coupled with a server. A network input/output device for the server receives a remote direct memory access (RDMA) command including a steering tag (S-Tag) from a client remote to the server. For these examples, the network input/output device forwards the RDMA command to a Non-Volatile Memory Express (NVMe) controller and access is provided to a storage medium based on an allocation scheme that assigned the S-Tag to the storage medium. In some other examples, an NVMe controller generates a memory mapping of one or more storage devices controlled by the NVMe controller to addresses for a base address register (BAR) on a Peripheral Component Interconnect Express (PCIe) bus. PCIe memory access commands received by the NVMe controller are translated based on the memory mapping to provide access to the storage device.

    Abstract translation: 示例包括客户端访问与服务器耦合的存储介质。 用于服务器的网络输入/输出设备从远程服务器的客户端接收包括转向标签（S-Tag）的远程直接存储器访问（RDMA）命令。 对于这些示例，网络输入/输出设备将RDMA命令转发到非易失性存储器Express（NVMe）控制器，并且基于将S-Tag分配给存储介质的分配方案向存储介质提供访问。 在其他一些示例中，NVMe控制器生成由NVMe控制器控制的一个或多个存储设备的存储器映射到外围组件互连Express（PCIe）总线上的基地址寄存器（BAR）的地址。 由NVMe控制器接收的PCIe存储器访问命令基于存储器映射进行转换，以提供对存储设备的访问。

    Techniques for use of vendor defined messages to execute a command to access a storage device
    10.
    发明授权
    Techniques for use of vendor defined messages to execute a command to access a storage device 有权
    使用供应商定义的消息执行访问存储设备的命令的技术

    公开(公告)号：US09467511B2

    公开(公告)日：2016-10-11

    申请号：US13743112

    申请日：2013-01-16

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Steen Larsen

    IPC: G06F13/12 ,  G06F15/167 ,  H04L29/08 ,  G06F21/80 ,  G06F21/44 ,  G06F21/79 ,  H04L29/06 ,  G06F3/06

    CPC classification number: G06F15/17331 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688 ,  G06F13/4282 ,  G06F15/167 ,  G06F21/44 ,  G06F21/79 ,  G06F21/80 ,  G06F2213/0026 ,  H04L67/1097 ,  H04L69/12 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Examples are disclosed for use of vendor defined messages to execute a command to access a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server for the client to access the storage device. For these examples, elements or components of the network input/output device may be capable of forwarding the command either directly to a Non-Volatile Memory Express (NVMe) controller that controls the storage device or to a manageability module coupled between the network input/out device and the NVMe controller. Vendor specific information may be forwarded with the command and used by either the NVMe controller or the manageability module to facilitate execution of the command. Other examples are described and claimed.

    Abstract translation: 公开了使用供应商定义的消息来执行访问维护在服务器上的存储设备的命令的示例。 在一些示例中，耦合到服务器的网络输入/输出设备可以从远程服务器的客户端接收命令，以使客户端访问存储设备。 对于这些示例，网络输入/输出设备的元件或组件可能能够将命令直接转发到控制存储设备的非易失性存储器Express（NVMe）控制器或耦合在网络输入/ 输出设备和NVMe控制器。 供应商的具体信息可以使用命令转发，并由NVMe控制器或可管理性模块使用，以便于执行命令。 其他的例子被描述和要求保护。

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