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公开(公告)号：US09612652B2
公开(公告)日：2017-04-04
申请号：US13631907
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Efraim Rotem , Jawad Haj-Yihia , Ohad Falik
CPC classification number: G06F1/3296 , G06F1/3203 , G06F1/3209 , G06F1/3215 , G06F1/3287 , Y02D10/171
Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
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公开(公告)号：US09026682B2
公开(公告)日：2015-05-05
申请号：US13713635
申请日：2012-12-13
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US09098415B2
公开(公告)日：2015-08-04
申请号：US13691016
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US20150149683A9
公开(公告)日：2015-05-28
申请号：US13691016
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC: G06F13/40
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US11074191B2
公开(公告)日：2021-07-27
申请号：US15803244
申请日：2017-11-03
Applicant: Intel Corporation
Inventor： Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B. Crossland , Ohad Falik
IPC: G06F12/00 , G06F12/1009 , G06F12/1027 , G06F12/10 , G06F12/1036
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US09973335B2
公开(公告)日：2018-05-15
申请号：US13839080
申请日：2013-03-15
Applicant: INTEL CORPORATION
Inventor： Ben-Zion Friedman , Eliezer Tamir , Eliel Louzoun , Ohad Falik
CPC classification number: H04L9/0618 , G06F21/72 , H04L63/0485
Abstract: Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.
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公开(公告)号：US09892069B2
公开(公告)日：2018-02-13
申请号：US14800419
申请日：2015-07-15
Applicant: Intel Corporation
Inventor： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
CPC classification number: G06F13/24 , G06F9/4812
Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.
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公开(公告)号：US09158703B2
公开(公告)日：2015-10-13
申请号：US14312669
申请日：2014-06-23
Applicant: Intel Corporation
Inventor： Ohad Falik , Ben-Zion Friedman , Jack Doweck , Eliezer Weissmann , James B. Crossland
CPC classification number: G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
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公开(公告)号：US09116869B2
公开(公告)日：2015-08-25
申请号：US14467604
申请日：2014-08-25
Applicant: Intel Corporation
Inventor： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
CPC classification number: G06F13/24 , G06F9/4812
Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.
Abstract translation: 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，装置包括查找逻辑和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。
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10.发明授权公开(公告)号：US08935514B2
公开(公告)日：2015-01-13
申请号：US14012344
申请日：2013-08-28
Applicant: Intel Corporation
Inventor： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
CPC classification number: G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
Abstract: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。 代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。 描述和要求保护其他实施例。
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