公开(公告)号：US20150028449A1

公开(公告)日：2015-01-29

申请号：US13950323

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L49/02 ,  H01L21/762

CPC classification number: H01L21/76224 ,  B82Y30/00 ,  B82Y40/00 ,  H01G4/008 ,  H01G4/012 ,  H01G4/33 ,  H01L28/82 ,  H01L29/0665 ,  H01L29/0688 ,  H01L29/16 ,  H01L29/6609 ,  H01L29/861 ,  Y02T10/7022

Abstract: Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically connected one to another and to the first conductive plate. The supercapacitor may also include a dielectric formed on surfaces of the 3D aggregate of sintered nanoparticles. The supercapacitor may further include a second electrode comprising a solid second conductor that fills interstices between surfaces of the dielectric and electrically connects to a second conductive plate of a solid second conductor, disposed above an outermost portion of the dielectric.

Abstract translation: 制造超级电容器的结构和方法可以包括第一电极，其包括第一导电板和电连接到第一导电板的烧结纳米粒子的三维（3D）聚集体。 超级电容器还可以包括形成在烧结纳米颗粒的3D聚集体的表面上的电介质。 超级电容器还可以包括第二电极，该第二电极包括固体第二导体，其填充介质的表面之间的间隙，并且电连接到置于电介质的最外部分之上的固体第二导体的第二导电板。

公开(公告)号：US08903210B2

公开(公告)日：2014-12-02

申请号：US13872385

申请日：2013-04-29

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B6/26 ,  G02B6/12 ,  G02B6/13 ,  G02B6/35

CPC classification number: G02B6/4214 ,  G02B6/12002 ,  G02B6/125 ,  G02B6/136 ,  G02B6/3504 ,  G02B2006/12061 ,  G02B2006/12119 ,  G02B2006/12123 ,  G02B2006/12147

Abstract: An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion.

Abstract translation: 光波导结构可以包括具有顶表面的电介质层，光波导结构和嵌入电介质层内的光耦合器。 光耦合器可以具有耦合到电介质层的顶表面的大致垂直部分和耦合到光波导结构的基本上水平的部分。 大致垂直部分和大致水平部分被弯曲部分分开。

公开(公告)号：US20140321802A1

公开(公告)日：2014-10-30

申请号：US13872396

申请日：2013-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/4214

Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.

Abstract translation: 光波导结构可以包括位于半导体结构内的光波导结构和光耦合器。 光耦合器可以包括位于半导体结构的电互连区域内的金属结构，由此金属结构从电互连区域的顶表面以基本弯曲的形状向下延伸并且耦合到光波导结构。 光耦合器还可以包括在金属结构内限定的光信号引导区域，由此光耦合器从顶表面接收光信号并将光信号耦合到光波导结构，使得光信号传播在 顶表面并且在光波导结构处基本上水平。

公开(公告)号：US08564067B2

公开(公告)日：2013-10-22

申请号：US13772402

申请日：2013-02-21

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L21/70

CPC classification number: H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US20130210227A1

公开(公告)日：2013-08-15

申请号：US13851709

申请日：2013-03-27

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.