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71.发明授权Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level 有权半导体器件和相关布局具有由具有通过单互连级别的栅电极连接的六个线性导电段形成的晶体管公开(公告)号：US07910959B2
公开(公告)日：2011-03-22
申请号：US12572077
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.
摘要翻译： 半导体器件的单元布局包括包括多个扩散区布局形状的扩散级布局。 电池布局还包括限定为包括仅在第一平行方向上延伸的线性布局特征的栅极电平布局。 在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由 半导体器件制造能力。 栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。 电池布局还包括多个互连电平布局，每个互连电平布局被定义为在电池的栅电极电平以上的相应互连电平内对导电特征进行图案化。
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72.发明授权公开(公告)号：US07901953B2
公开(公告)日：2011-03-08
申请号：US12205871
申请日：2008-09-06
IPC分类号： H01L21/66
CPC分类号： G01R31/2858 , G01R31/2853 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： In some aspects, a method is provided for detecting a void in a test structure that comprises (a) measuring a resistance of the test structure; (b) applying a stress to the test structure at increasing levels until at least one of: (i) the measured resistance of the test structure exceeds a predetermined resistance threshold; and (ii) the stress level reaches a predetermined stress maximum; (c) detecting a void if the measured resistance of the test structure exceeds the predetermined resistance threshold; and (d) determining that the test structure is void free if the stress level reaches the predetermined stress maximum without the measured resistance of the test structure exceeding the predetermined resistance threshold. Numerous other aspects are provided.
摘要翻译： 在一些方面，提供了一种用于检测测试结构中的空隙的方法，其包括：（a）测量测试结构的电阻; （b）以增加的水平向测试结构施加应力，直到以下至少一个：（i）测试结构的测量电阻超过预定电阻阈值; 和（ii）应力水平达到预定的应力最大值; （c）如果测试结构的测量电阻超过预定电阻阈值，则检测空隙; 以及（d）如果应力水平达到预定的应力最大值而确定测试结构无空隙，而测试结构的测量电阻不超过预定电阻阈值。 提供了许多其他方面。
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73.发明申请Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors 有权具有Sub-193纳米尺寸栅电极的半导体器件的单元由矩形形状的栅电极形成的导电结构布局特征和等量的PMOS和NMOS晶体管公开(公告)号：US20100032724A1
公开(公告)日：2010-02-11
申请号：US12572022
申请日：2009-10-01
IPC分类号： H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括形成为包括多个扩散区域的衬底部分，所述扩散区域包括至少一个p型扩散区域和至少一个由非有源区域彼此分离的n型扩散区域。 电池包括包括多个导电特征的栅电极层，该导电特征限定为只在第一平行方向上延伸。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 在栅电极水平内的五波长光刻相互作用半径内的导电特征的宽度尺寸小于193纳米的光的波长。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 该单元包括相等数量的PMOS和NMOS晶体管器件。 电池还包括形成在栅极电极上方的多个互连电平。
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74.发明申请Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors 有权半导体器件部分具有由直线形栅极电极形成的栅极电极导电结构布局特征，具有最小端到端间距并具有至少八个晶体管公开(公告)号：US20100032722A1
公开(公告)日：2010-02-11
申请号：US12567602
申请日：2009-09-25
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.
摘要翻译： 半导体器件包括其中限定有多个扩散区的衬底部分。 该半导体器件包括包含多个导电特征的栅极电平区域，该导电特征被限定为只在第一平行方向上延伸。 在第一并行方向上共享公共线路的相同数量的导电特征的相邻的导电特征由相应的起始布局特征制成，所述各个起始布局特征通过端对端间隔彼此分离，所述端对端间隔具有在 栅极电极水平区域并且被最小化到半导体器件制造能力允许的程度。 栅极电极区域内的一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。 栅极电极区域中的PMOS和NMOS晶体管器件的总数大于或等于8。
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75.发明申请Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors 有权具有Sub-193纳米级的半导体器件部分 - 由线性形栅极电极形成的栅极电极导体结构由最小端到端间隔定义并具有等量的PMOS和NMOS晶体管的布局特征公开(公告)号：US20100032721A1
公开(公告)日：2010-02-11
申请号：US12567597
申请日：2009-09-25
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
摘要翻译： 半导体器件包括其中限定有多个扩散区的衬底部分。 在基板部分上方形成栅极电平区域，以包括仅在第一平行方向上延伸的导电特征。 共享公共线程的相邻的导电特征由相应的起始布局特征制成，该特征通过栅极电极水平区域上的基本相等和最小尺寸的端到端间隔彼此分开。 在5波长光刻相互作用半径内的导电特征的宽度小于在其制造的光刻工艺中使用的193纳米波长的光。 一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。 多个PMOS晶体管器件等于栅电极电平区域中的NMOS晶体管器件的数量。
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76.发明申请Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication 有权控制半导体晶片布局和制造中微加载变化的方法公开(公告)号：US20100031211A1
公开(公告)日：2010-02-04
申请号：US12512932
申请日：2009-07-30
申请人： Brian Reed , Michael C. Smayling
发明人： Brian Reed , Michael C. Smayling
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.
摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并随后从晶片上移除留下期望的永久结构。
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77.发明申请Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing 有权具有直线形栅极电极的半导体器件的单元布局具有最小端到端间隔的至少四个栅极电极轨迹定义的布局特征公开(公告)号：US20100023906A1
公开(公告)日：2010-01-28
申请号：US12572068
申请日：2009-10-01
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.
摘要翻译： 半导体器件的单元布局包括包括多个扩散区布局形状的扩散级布局。 电池布局还包括限定为包括仅在第一平行方向上延伸的线性布局特征的栅极电平布局。 在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由 半导体器件制造能力。 栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。 电池布局还包括多个互连电平布局，每个互连电平布局被定义为在电池的栅电极电平以上的相应互连电平内对导电特征进行图案化。
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78.发明申请Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks 有权具有栅电极的半导体器件的单元由矩形形状的栅电极形成的栅电极导电结构布置特征沿着至少四栅极电极轨迹公开(公告)号：US20100019280A1
公开(公告)日：2010-01-28
申请号：US12571343
申请日：2009-09-30
IPC分类号： H01L27/04
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 公开了一种半导体器件的电池，其包括扩散级，其包括由非活性区域分开的多个扩散区域。 电池还包括栅极电极级，其包括限定为仅在第一平行方向上延伸的多个导电特征。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 栅极电极级包括沿着沿着第一平行方向的至少四个不同的虚拟线限定的导电特征。 电池还包括形成在栅极电极上方的多个互连电平。
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79.发明申请Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors 有权包括具有限制门极电极布局的单元格布局的半导体器件布局线性形栅极电极布局特征定义为最小端到端间隔和至少八个晶体管公开(公告)号：US20100017766A1
公开(公告)日：2010-01-21
申请号：US12567528
申请日：2009-09-25
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region includes a diffusion level layout including diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A total number of PMOS and NMOS transistor devices in the restricted layout region is greater than or equal to eight. The restricted layout region corresponds to an entire gate electrode level of a cell layout.
摘要翻译： 限制布局区域包括扩散级布局，其包括限定至少一个p型扩散区域的扩散区域布局形状和由中心非活性区域分隔开的至少一个n型扩散区域。 栅电极层布局被限定在衬底部分上方，以包括仅在第一平行方向上延伸的线性布局特征。 在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由 半导体器件制造能力。 限制布局区域中的PMOS和NMOS晶体管器件的总数大于或等于8。 限制布局区域对应于单元布局的整个栅电极层。
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80.发明申请Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors 有权具有由矩形形栅极电极形成的栅电极导电结构的半导体器件的单元布局特性和等量的PMOS和NMOS晶体管公开(公告)号：US20100012986A1
公开(公告)日：2010-01-21
申请号：US12571998
申请日：2009-10-01
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括形成为包括多个扩散区域的基板部分，该多个扩散区域包括至少一个p型扩散区域和至少一个由一个或多个非有源区域彼此分离的n型扩散区域。 电池包括包括多个导电特征的栅电极层，该导电特征限定为只在第一平行方向上延伸。 栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 多个PMOS晶体管器件等于电池栅极电平中的NMOS晶体管器件的数量。 电池还包括形成在栅极电极上方的多个互连电平。
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