公开(公告)号：US07940581B2

公开(公告)日：2011-05-10

申请号：US12861026

申请日：2010-08-23

申请人： Igor Arsovski ,  Michael T. Fragano ,  Robert M. Houle

发明人： Igor Arsovski ,  Michael T. Fragano ,  Robert M. Houle

IPC分类号： G11C7/06

CPC分类号： G11C8/16 ,  G11C11/419

摘要： A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.

摘要翻译： 一种用于感测静态随机存取存储器（SRAM）内的存储单元的内容的方法包括当存储单元未被访问时，将与存储单元相关联的位线保持在零电压电位; 在存储器单元的访问期间将位线激励到不同于零电压电位的第一电压电位; 以及当相关联的位线已经达到第一电压电位时感测存储器单元的内容。

公开(公告)号：US20110088005A1

公开(公告)日：2011-04-14

申请号：US12576275

申请日：2009-10-09

申请人： Igor Arsovski

发明人： Igor Arsovski

IPC分类号： G06F17/50

CPC分类号： G11C15/04

摘要： A method for producing a configurable content-addressable memory (CAM) cell design, in which the method includes: inputting the configurable CAM cell design to a computer, the configurable CAM cell design capable of being configured as one of a binary CAM design and a ternary CAM design, depending on connections of a metal overlay; selecting one of a first metal overlay design for the binary CAM design and a second metal overlay design for a ternary CAM design; if the first metal overlay design is selected, then combining the first metal overlay design with the configurable CAM cell design to produce a binary CAM design including two binary CAM cells with a single search port, and outputting the binary CAM design; and if the second metal overlay design is selected, then combining the second metal overly design with the configurable CAM cell design to produce a ternary CAM design including a single ternary CAM cell with two search ports, and outputting the ternary CAM design by the computer.

摘要翻译： 一种用于生成可配置内容寻址存储器（CAM）单元设计的方法，其中所述方法包括：将可配置CAM单元设计输入到计算机，所述可配置CAM单元设计能够被配置为二进制CAM设计和 三元CAM设计，取决于金属覆盖层的连接; 选择用于二进制CAM设计的第一金属覆盖设计和用于三元CAM设计的第二金属覆盖设计; 如果选择第一个金属覆盖设计，则将第一金属覆盖设计与可配置的CAM单元设计相结合，以产生包括具有单个搜索端口的两个二进制CAM单元的二进制CAM设计，并输出二进制CAM设计; 并且如果选择第二金属覆盖设计，则将第二金属过度设计与可配置的CAM单元设计组合以产生包括具有两个搜索端口的单个三元CAM单元并由计算机输出三元CAM设计的三元CAM设计。

公开(公告)号：US07859878B2

公开(公告)日：2010-12-28

申请号：US12110375

申请日：2008-04-28

申请人： Igor Arsovski ,  Kerry Bernstein

发明人： Igor Arsovski ,  Kerry Bernstein

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括内容可寻址存储器（CAM）装置，其具有排列成字线方向的存储单元阵列和排列在位线方向上的列，并且配置有比较电路 将存储在阵列中的数据与存储在阵列的每一行和列中的数据进行比较，同时在阵列的每一行和列上指示匹配结果，从而产生二维的基于矩阵的数据比较操作。

公开(公告)号：US07830727B2

公开(公告)日：2010-11-09

申请号：US12135237

申请日：2008-06-09

申请人： Igor Arsovski ,  Michael Thomas Fragano ,  Robert Maurice Houle

发明人： Igor Arsovski ,  Michael Thomas Fragano ,  Robert Maurice Houle

IPC分类号： G11C7/06

CPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413

摘要： An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.

摘要翻译： 在使用预放电位线的多端口静态随机存取存储器（SRAM）中用于低功率，单端感测的装置和方法包括：当存储器单元为存储单元时，将与存储器单元相关联的位线保持在零电压电位 没有被访问 当存储器单元被访问时，释放位线保持在零电压电位; 在存储单元访问期间将位线充电到比零电压电位大的第一电压电位，其中在访问存储器单元之后的第一预定时间段内将位线充电到第一电压电位， 开始了 以及在所述存储器单元的访问期间感测所述存储器单元的内容，其中在开始访问所述存储器单元之后的第二预定时间段内存储单元内容的感测发生。

公开(公告)号：US07826288B2

公开(公告)日：2010-11-02

申请号：US11684225

申请日：2007-03-09

申请人： Igor Arsovski ,  Harold Pilo ,  Michael A. Ziegerhofer

发明人： Igor Arsovski ,  Harold Pilo ,  Michael A. Ziegerhofer

IPC分类号： G11C29/00 ,  G11C7/06 ,  G11C11/413 ,  G11C29/50 ,  G11C29/06 ,  G11C11/412

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/028

摘要： In a method for reducing and/or eliminating mismatch in one or more devices that require a balanced state (e.g., in cross-coupled transistors in each memory cell and/or sense amp in a memory array), the bias (i.e., the preferred state) of each of the devices is determined. Then, a burn-in process is initiated, during which an individually selected state is applied to each of the devices. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.

摘要翻译： 在用于减少和/或消除需要平衡状态的一个或多个器件（例如，在每个存储器单元中的交叉耦合晶体管和/或存储器阵列中的读出放大器）中的失配的方法中，偏差（即，优选的 状态）被确定。 然后，启动老化过程，在此期间，将单独选择的状态应用于每个设备。 这使得设备远离其优选的状态并且朝向平衡状态。 在老化过程中定期重新评估偏差，以避免过度校正。 通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。

公开(公告)号：US07688611B2

公开(公告)日：2010-03-30

申请号：US12047209

申请日：2008-03-12

申请人： Igor Arsovski ,  Rahul K. Nadkami ,  Reid A. Wistort

发明人： Igor Arsovski ,  Rahul K. Nadkami ,  Reid A. Wistort

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/02

摘要： This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.

摘要翻译： 该专利描述了用于在内容寻址存储器（CAM）中异步地切换搜索线以提高CAM速度并降低CAM噪声而不影响其功率性能的方法。 这是通过在发起搜索之前重置匹配线，然后将搜索词应用于搜索线来实现的。 提供参考匹配线以产生用于搜索操作的定时，并为SL上的搜索数据的异步应用提供定时。 通过可编程延迟元件在SL上搜索数据应用的交错来实现额外的降噪。

公开(公告)号：US20090141527A1

公开(公告)日：2009-06-04

申请号：US11949063

申请日：2007-12-03

申请人： Igor Arsovski ,  Kerry Bernstein

发明人： Igor Arsovski ,  Kerry Bernstein

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

摘要翻译： 一种内容可寻址存储器（CAM）装置，包括排列成字线方向的存储单元阵列和排列在位线方向上的列，以及比较电路，被配置为将呈现给阵列的数据与存储在每行和列中的数据进行比较 并且同时指示阵列的每一行和列上的匹配结果，从而导致二维的基于矩阵的数据比较操作。

公开(公告)号：US20060104100A1

公开(公告)日：2006-05-18

申请号：US11320746

申请日：2005-12-30

申请人： Igor Arsovski ,  Ali Sheikholeslami

发明人： Igor Arsovski ,  Ali Sheikholeslami

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

公开(公告)号：US08654594B2

公开(公告)日：2014-02-18

申请号：US13403252

申请日：2012-02-23

申请人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

IPC分类号： G11C11/412

CPC分类号： G11C5/147 ,  G11C11/417

摘要： An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.

摘要翻译： 集成电路结构包括静态随机存取存储器（SRAM）结构和逻辑电路。 电源可操作地连接到SRAM结构，并且向SRAM结构提供第一电压。 电压限制器可操作地连接到电源。 电压限制器包括可操作地连接到电源的开关装置。 开关器件接收提供给SRAM结构外部结构的第一电压和第二电压。 电阻元件可操作地连接到开关装置。 开关装置将电阻元件连接到电源。 电阻元件被选择为当第一电压和第二电压之间的差大于开关器件的电压阈值时，使能从开关器件到逻辑电路的输出。

公开(公告)号：US20130234754A1

公开(公告)日：2013-09-12

申请号：US13414976

申请日：2012-03-08

申请人： Igor Arsovski ,  Robert M. Houle

发明人： Igor Arsovski ,  Robert M. Houle

IPC分类号： H03K19/173 ,  H03K19/00

CPC分类号： H03K19/003 ,  G11C11/419

摘要： Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

摘要翻译： 提供了用于配置集成电路的方法和结构，所述集成电路包括被划分为具有相应的电力辅助的行的重复单元和相应的操作辅助。 一种方法包括配置银行而无需电力辅助和操作辅助。 该方法还包括基于在用相应的操作辅助配置银行之后，确定弱电池保留在银行中的银行的电力辅助。