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17 条记录 (耗时 0.012 秒)

    SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same
    1.
    发明申请
    SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same 有权
    SRAM具有可调节字节上位电压以协助位单元稳定性和设计结构

    公开(公告)号：US20120075918A1

    公开(公告)日：2012-03-29

    申请号：US12892160

    申请日：2010-09-28

    申请人： Igor Arsovski ,  John A. Fifield ,  Robert M. Houle ,  Harold Pilo

    发明人： Igor Arsovski ,  John A. Fifield ,  Robert M. Houle ,  Harold Pilo

    IPC分类号： G11C11/00 ,  G11C8/08 ,  G06F17/50

    CPC分类号： G11C8/08 ,  G11C11/413

    摘要： An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.

    摘要翻译： 一种集成电路，包括含有字线的存储器和具有SRAM存储元件并连接到字线的位单元。 提供了字线上级辅助电路，其设计和配置为提供多个可选择的电压值，其可被选择以提供在存储器读周期和/或写周期期间提供给位单元的字线上电压。 在一个示例中，所选择的电压值基于所制造的比特单元的表征来选择，以便降低位单元经历稳定性故障的可能性。

    Method for low power sensing in a multi-port SRAM using pre-discharged bit lines
    2.
    发明授权
    Method for low power sensing in a multi-port SRAM using pre-discharged bit lines 有权
    使用预放电位线的多端口SRAM中的低功率感测方法

    公开(公告)号：US07940581B2

    公开(公告)日：2011-05-10

    申请号：US12861026

    申请日：2010-08-23

    申请人： Igor Arsovski ,  Michael T. Fragano ,  Robert M. Houle

    发明人： Igor Arsovski ,  Michael T. Fragano ,  Robert M. Houle

    IPC分类号： G11C7/06

    CPC分类号： G11C8/16 ,  G11C11/419

    摘要： A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.

    摘要翻译： 一种用于感测静态随机存取存储器（SRAM）内的存储单元的内容的方法包括当存储单元未被访问时，将与存储单元相关联的位线保持在零电压电位; 在存储器单元的访问期间将位线激励到不同于零电压电位的第一电压电位; 以及当相关联的位线已经达到第一电压电位时感测存储器单元的内容。

    FINE GRANULARITY POWER GATING
    5.
    发明申请
    FINE GRANULARITY POWER GATING 有权
    精细粒度功率增益

    公开(公告)号：US20130148455A1

    公开(公告)日：2013-06-13

    申请号：US13315604

    申请日：2011-12-09

    申请人： Robert M. Houle ,  Steven H. Lamphier ,  Harold Pilo

    发明人： Robert M. Houle ,  Steven H. Lamphier ,  Harold Pilo

    IPC分类号： G11C5/14

    CPC分类号： G11C11/413 ,  G11C8/08 ,  G11C8/10

    摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.

    摘要翻译： 描述了一种用于提供存储器阵列的精细粒度电源门控的方法。 在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。 激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线 存储器阵列中的剩余行被提供电源门控电压值。

    Fine granularity power gating
    6.
    发明授权
    Fine granularity power gating 有权
    细粒度电源门控

    公开(公告)号：US08611169B2

    公开(公告)日：2013-12-17

    申请号：US13315604

    申请日：2011-12-09

    申请人： Robert M. Houle ,  Steven H. Lamphier ,  Harold Pilo

    发明人： Robert M. Houle ,  Steven H. Lamphier ,  Harold Pilo

    IPC分类号： G11C5/14

    CPC分类号： G11C11/413 ,  G11C8/08 ,  G11C8/10

    摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.

    摘要翻译： 描述了一种用于提供存储器阵列的精细粒度电源门控的方法。 在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。 激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线 存储器阵列中的剩余行被提供电源门控电压值。

    Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability
    7.
    发明申请
    Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权
    用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量

    公开(公告)号：US20120075919A1

    公开(公告)日：2012-03-29

    申请号：US12892191

    申请日：2010-09-28

    申请人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

    发明人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413 ,  G11C8/08

    摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.

    摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

    Digital clock signal multiplier circuit
    8.
    发明授权
    Digital clock signal multiplier circuit 失效
    数字时钟信号乘法电路

    公开(公告)号：US5422835A

    公开(公告)日：1995-06-06

    申请号：US98189

    申请日：1993-07-28

    申请人： Robert M. Houle ,  Dac C. Pham

    发明人： Robert M. Houle ,  Dac C. Pham

    IPC分类号： G06F1/08 ,  G06F7/68 ,  H03B19/00 ,  H03K5/00 ,  H03L7/081 ,  H03L7/16 ,  G06F7/52

    CPC分类号： G06F1/08 ,  G06F7/68 ,  H03K5/00006 ,  H03L7/0814 ,  H03L7/16 ,  H03B19/00

    摘要： A digital clock signal multiplier circuit for generating an on-chip clock signal having a higher frequency than a system clock signal. A variable delay line, coupled to receive the system clock signal, is partitioned into (N) equal segments with each segment having multiple delay elements. Each of the delay elements is tapped to allow selective output of a corresponding delay signal. Multiple control switches, each associated with one of the delay elements, provide selective control for issuance of only one delay signal from each segment of the variable delay line. Delay signals selected for output are symmetrically offset and are fed to (N) pulse generators for the production of (N) pulse signals of duration substantially less than the period of the external clock signal. An output generator is coupled to receive the pulse signals output from the (N) pulse generators and produce therefrom the internal clock signal of desired frequency. Control circuitry selects the delay signals output from the (N) equal segments via appropriate activation of the associated control switches.

    摘要翻译： 一种数字时钟信号乘法器电路，用于产生频率高于系统时钟信号的片上时钟信号。 耦合以接收系统时钟信号的可变延迟线被划分为具有多个延迟元件的每个段的（N）个相等的段。 每个延迟元件被抽头以允许选择性地输出相应的延迟信号。 每个与延迟元件中的一个相关联的多个控制开关提供对从可变延迟线的每个段发出仅一个延迟信号的选择性控制。 选择用于输出的延迟信号对称偏移并馈送到（N）个脉冲发生器，用于产生持续时间显着小于外部时钟信号周期的（N）个脉冲信号。 输出发生器被耦合以接收从（N）个脉冲发生器输出的脉冲信号，从而产生所需频率的内部时钟信号。 控制电路通过相应的控制开关的适当激活来选择从（N）相等的段输出的延迟信号。

    MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTURES THEREOF
    9.
    发明申请
    MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTURES THEREOF 失效
    重复结构及其结构的主要优势方案

    公开(公告)号：US20130234754A1

    公开(公告)日：2013-09-12

    申请号：US13414976

    申请日：2012-03-08

    申请人： Igor Arsovski ,  Robert M. Houle

    发明人： Igor Arsovski ,  Robert M. Houle

    IPC分类号： H03K19/173 ,  H03K19/00

    CPC分类号： H03K19/003 ,  G11C11/419

    摘要： Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

    摘要翻译： 提供了用于配置集成电路的方法和结构，所述集成电路包括被划分为具有相应的电力辅助的行的重复单元和相应的操作辅助。 一种方法包括配置银行而无需电力辅助和操作辅助。 该方法还包括基于在用相应的操作辅助配置银行之后，确定弱电池保留在银行中的银行的电力辅助。