公开(公告)号：US20240020447A1

公开(公告)日：2024-01-18

申请号：US18202929

申请日：2023-05-28

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

CPC classification number: G06F30/3323 ,  G06F11/0754 ,  G06F11/3466 ,  G06F30/39

Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

公开(公告)号：US20230205621A1

公开(公告)日：2023-06-29

申请号：US18114963

申请日：2023-02-27

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F11/07 ,  G06F30/30 ,  G06F21/52

CPC classification number: G06F11/0793 ,  G06F30/30 ,  G06F11/073 ,  G06F21/52 ,  G06F11/0736 ,  G06F11/0754 ,  G06F30/392

Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

公开(公告)号：US20230033403A1

公开(公告)日：2023-02-02

申请号：US17961497

申请日：2022-10-06

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F9/32 ,  G06F9/38 ,  G06F11/00 ,  G06F9/30

Abstract: Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

公开(公告)号：US20220138389A1

公开(公告)日：2022-05-05

申请号：US17573611

申请日：2022-01-11

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

公开(公告)号：US20210294690A1

公开(公告)日：2021-09-23

申请号：US17338538

申请日：2021-06-03

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F11/07 ,  G06F30/30

Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

公开(公告)号：US10963611B2

公开(公告)日：2021-03-30

申请号：US16414594

申请日：2019-05-16

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F30/30 ,  G06F30/39 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F119/18

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

公开(公告)号：US10929583B2

公开(公告)日：2021-02-23

申请号：US16441473

申请日：2019-06-14

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F17/50 ,  G06F30/3312 ,  G01R31/317 ,  G06F30/398 ,  G06F30/3323

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

公开(公告)号：US10366187B2

公开(公告)日：2019-07-30

申请号：US15404414

申请日：2017-01-12

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F17/50 ,  G01R31/317

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

公开(公告)号：US10359825B2

公开(公告)日：2019-07-23

申请号：US15351644

申请日：2016-11-15

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  John Alexander Osborne Netterville ,  Ashish Darbari

IPC: G06F17/50 ,  G06F1/28 ,  G06F1/3234 ,  G06F1/12

Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.

公开(公告)号：US10067896B2

公开(公告)日：2018-09-04

申请号：US15680755

申请日：2017-08-18

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F13/364 ,  G06F13/42 ,  G06F9/46 ,  G06F13/36 ,  G06F5/00 ,  G06F11/28 ,  G06F11/30

Abstract: Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.