公开(公告)号：US20170126400A1

公开(公告)日：2017-05-04

申请号：US15401877

申请日：2017-01-09

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

IPC: H04L9/06 ,  G06F9/30 ,  G06F21/72

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72

Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

公开(公告)号：US09614544B2

公开(公告)日：2017-04-04

申请号：US14671462

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Sean M. Gulley ,  Gilbert M. Wolrich

IPC: H03M7/00 ,  H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  H03M7/30 ,  H03M7/46

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

公开(公告)号：US09569210B2

公开(公告)日：2017-02-14

申请号：US15203610

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到所述第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）置换逻辑电路，其具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入。

公开(公告)号：US20160034282A1

公开(公告)日：2016-02-04

申请号：US14880166

申请日：2015-10-09

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

Abstract translation: 说明和逻辑提供SIMD安全散列圆切片功能。 一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分 圆周运算，旋转设定部分旋转设定。 处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。 该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。 其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

公开(公告)号：US09027104B2

公开(公告)日：2015-05-05

申请号：US13843141

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

IPC: G06F21/72 ,  H04L9/06

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72

Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

Abstract translation: 方面的方法包括接收指令。 该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。 该指令指示第二打包数据的第二来源。 第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。 该方法还包括响应于指令将结果存储在由指令指示的目的地中。 结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

公开(公告)号：US08924741B2

公开(公告)日：2014-12-30

申请号：US13731004

申请日：2012-12-29

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

IPC: H04L29/06 ,  G06F21/60

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

Abstract translation: 说明和逻辑提供SIMD安全散列圆切片功能。 一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分 圆周运算，旋转设定部分旋转设定。 处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。 该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。 其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

公开(公告)号：US20140122839A1

公开(公告)日：2014-05-01

申请号：US13997186

申请日：2011-12-22

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US11550582B2

公开(公告)日：2023-01-10

申请号：US16903542

申请日：2020-06-17

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/0875 ,  G06F12/1027 ,  G09C1/00 ,  H04L9/32 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20220224510A1

公开(公告)日：2022-07-14

申请号：US17706288

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Eugene M. Kishinevsky ,  Uday Savagaonkar ,  Alpa T. Narendra Trivedi ,  Siddhartha Chhabra ,  Baiju V. Patel ,  Men Long ,  Kirk S. Yap ,  David M. Durham

IPC: H04L9/06 ,  G06F12/14 ,  G09C1/00 ,  G06F21/85 ,  G06F21/60

Abstract: Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.

公开(公告)号：US11303438B2

公开(公告)日：2022-04-12

申请号：US16928558

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.