公开(公告)号：US12164971B2

公开(公告)日：2024-12-10

申请号：US18301733

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L61/59 ,  H04L67/2885

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US11715174B2

公开(公告)日：2023-08-01

申请号：US17685445

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F11/07 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/3887 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5083 ,  G06F9/5088 ,  G06F11/0793 ,  G06F2209/5017 ,  G06T2200/28 ,  G06T2210/52 ,  Y02D10/00

Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

公开(公告)号：US11656916B2

公开(公告)日：2023-05-23

申请号：US17361932

申请日：2021-06-29

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L67/2885 ,  H04L61/59

CPC classification number: G06F9/5077 ,  G06F9/5038 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L61/59 ,  H04L67/2885 ,  H04T2001/2093

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US11556437B2

公开(公告)日：2023-01-17

申请号：US16211950

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu Aggarwal ,  Nrupal Jani ,  Manasi Deval ,  Kiran Patil ,  Parthasarathy Sarangam ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F9/455 ,  G06F9/46 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/48

Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.

公开(公告)号：US11474916B2

公开(公告)日：2022-10-18

申请号：US16211955

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu Aggarwal ,  Nrupal Jani ,  Manasi Deval ,  Kiran Patil ,  Parthasarathy Sarangam ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/455 ,  G06F9/48

Abstract: Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.

公开(公告)号：US11281500B2

公开(公告)日：2022-03-22

申请号：US16062568

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Jiajun Xu ,  Kun Tian ,  Zhiyuan Lv ,  Xiaowei Wang

IPC: G06F3/00 ,  G06F9/50 ,  G06T1/20 ,  G06F9/455 ,  H04L43/50 ,  H04L41/0896

Abstract: An apparatus and method are described for intelligent cloud based testing of graphics hardware and software. For example, one embodiment of an apparatus comprises: a hardware pool comprising a plurality of test machines to perform cloud-based graphics validation operations; a virtual resource pool comprising data associated a plurality of different graphics hardware resources; a resource manager to coordinate between the hardware pool and the virtual resource pool to cause one or more virtual machines (VMs) to be executed on one or more of the test machines using resources from the virtual resource pool; and a task dispatcher to dispatch graphics validation tasks to the VMs responsive to user input.

公开(公告)号：US11270406B2

公开(公告)日：2022-03-08

申请号：US17099118

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/48 ,  G06T1/20 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.

公开(公告)号：US11269782B2

公开(公告)日：2022-03-08

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun Tian ,  Xiao Zheng ,  Ashok Raj ,  Sanjay Kumar ,  Rajesh Sankaran

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

公开(公告)号：US11232536B2

公开(公告)日：2022-01-25

申请号：US16791514

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/60 ,  G06T1/20 ,  G06F8/41 ,  G06F12/0862

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US20210194828A1

公开(公告)日：2021-06-24

申请号：US17114304

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Shaopeng He ,  Jingjing Wu ,  Haitao Kang ,  Yadong Li ,  Kun Tian

IPC: H04L12/931 ,  H04L12/801 ,  G06F9/455

Abstract: Methods and apparatus for smart switch centered next generation cloud infrastructure architectures. Smart server switches are implemented in place of Top of Rack (ToR) switches and other switches in cloud infrastructure that include programmable switch chips (e.g., P4 switch chips) that are programmed via data plane runtime code executing on the switch chips to implement data plane operations in hardware in the switches. Meanwhile, control plane operations are implemented in the server switches via software executing on one or more CPUs or are implemented via servers that are coupled to the server switches. The data plane runtime code is used to forward data traffic and storage traffic in hardware via the programmable switch chips in a manner that offloads forwarding to hardware in virtualized cloud environments.