公开(公告)号：US11556436B2

公开(公告)日：2023-01-17

申请号：US16211930

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Nrupal Jani ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/455 ,  G06F9/48

Abstract: Examples may include a method of protecting memory and I/O transactions. The method includes allocating memory for an application, assigning a resource of a physical device to the application, assigning a process address space identifier to the assigned resource, creating a security enclave to protect the allocated memory of the application, and associating the security enclave with the process address space identifier to protect the allocated memory and the assigned resource.

公开(公告)号：US11513924B2

公开(公告)日：2022-11-29

申请号：US16211934

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Manasi Deval ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Alexander H. Duyck ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F9/455 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/48

Abstract: Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.

公开(公告)号：US20190042741A1

公开(公告)日：2019-02-07

申请号：US16142693

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Akeem Abodunrin ,  Lev Faerman ,  Scott Dubal ,  Suyog Kulkarni ,  Anjali Singhai Jain ,  Eliel Louzoun ,  Nrupal Jani ,  Yadong Li ,  Eliezer Tamir ,  Arvind Srinivasan ,  Ben-Zion Friedman

IPC: G06F21/55 ,  G06F13/40

Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.

公开(公告)号：US20180337850A1

公开(公告)日：2018-11-22

申请号：US15845107

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Dinesh Kumar ,  Christian Maciocco ,  Ren Wang ,  Neerav Parikh ,  John Fastabend ,  Iosif Gasparakis ,  David J. Harriman ,  Patrick L. Connor ,  Sanjeev Jain

IPC: H04L12/721 ,  H04L12/911 ,  H04L12/803 ,  H04L12/725 ,  H04L12/26

CPC classification number: H04L45/44 ,  H04L43/026 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/16 ,  H04L45/306 ,  H04L47/125 ,  H04L47/781

Abstract: Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.

公开(公告)号：US12117910B2

公开(公告)日：2024-10-15

申请号：US17868596

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Manasi Deval ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Alexander H. Duyck ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F3/06 ,  G06F9/455 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F11/2023 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/45558 ,  G06F9/4856 ,  G06F11/2007 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/17331 ,  G06F2009/45562 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45595 ,  G06F2201/805 ,  G06F2201/815 ,  G06F2213/0026

Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

公开(公告)号：US11573870B2

公开(公告)日：2023-02-07

申请号：US16211924

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Nrupal Jani ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F9/455 ,  G06F13/42 ,  G06F9/48 ,  G06F13/40 ,  G06F15/173 ,  G06F3/06 ,  G06F13/16 ,  G06F9/50 ,  G06F21/60 ,  G06F9/54

Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

公开(公告)号：US11531752B2

公开(公告)日：2022-12-20

申请号：US16142693

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Akeem Abodunrin ,  Lev Faerman ,  Scott Dubal ,  Suyog Kulkarni ,  Anjali Singhai Jain ,  Eliel Louzoun ,  Nrupal Jani ,  Yadong Li ,  Eliezer Tamir ,  Arvind Srinivasan ,  Ben-Zion Friedman

IPC: G06F21/55 ,  G06F13/40 ,  G06F21/53

Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.

公开(公告)号：US11025544B2

公开(公告)日：2021-06-01

申请号：US16435328

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Rajesh M. Sankaran ,  Ashok Raj ,  Nrupal Jani ,  Parthasarathy Sarangam ,  Robert O. Sharp

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US09742616B2

公开(公告)日：2017-08-22

申请号：US14580766

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Ilango Ganga ,  Daniel Daly ,  John Fastabend ,  Neerav Parikh ,  Elizabeth Kappler ,  Brian J. Skerry ,  Calin Gherghe ,  Sanjeev Jain ,  Ben-Zion Friedman

IPC: H04L29/06 ,  H04L12/54 ,  H04L12/931 ,  G06F9/455

CPC classification number: H04L29/0653 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L12/56 ,  H04L49/70 ,  H04L69/22

Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.

公开(公告)号：US11929927B2

公开(公告)日：2024-03-12

申请号：US17129756

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Rajesh M. Sankaran ,  Ashok Raj ,  Nrupal Jani ,  Parthasarathy Sarangam ,  Robert O. Sharp

IPC: G06F13/28 ,  G06F12/1081 ,  H04L45/60 ,  H04L45/74 ,  H04L49/90

CPC classification number: H04L45/742 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/9068

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.