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    Classifying features using a neurosynaptic system
    72.
    发明授权
    Classifying features using a neurosynaptic system 有权

    公开(公告)号：US10115054B2

    公开(公告)日：2018-10-30

    申请号：US14322778

    申请日：2014-07-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Rathinakumar Appuswamy ,  Steven K. Esser ,  Dharmendra S. Modha

    IPC分类号： G06N3/063 ,  G06N3/04

    摘要： Embodiments of the invention provide a method comprising receiving a set of features extracted from input data, training a linear classifier based on the set of features extracted, and generating a first matrix using the linear classifier. The first matrix includes multiple dimensions. Each dimension includes multiple elements. Elements of a first dimension correspond to the set of features extracted. Elements of a second dimension correspond to a set of classification labels. The elements of the second dimension are arranged based on one or more synaptic weight arrangements. Each synaptic weight arrangement represents effective synaptic strengths for a classification label of the set of classification labels. The neurosynaptic core circuit is programmed with synaptic connectivity information based on the synaptic weight arrangements. The core circuit is configured to classify one or more objects of interest in the input data.

    RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS
    78.
    发明申请
    RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 审中-公开
    神经网络可重构和可定制的一般用途电路

    公开(公告)号：US20160292569A1

    公开(公告)日：2016-10-06

    申请号：US15182485

    申请日：2016-06-14

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

    IPC分类号： G06N3/08 ,  G06N3/04

    CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

    摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

    摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。