公开(公告)号：US10984307B2

公开(公告)日：2021-04-20

申请号：US16427170

申请日：2019-05-30

申请人： International Business Machines Corporation

发明人： Filipp A. Akopyan ,  Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada

IPC分类号： G06N3/04

摘要： Embodiments of the invention provide a system and circuit interconnecting peripheral devices to neurosynaptic core circuits. The neurosynaptic system includes an interconnect that includes different types of communication channels. A device connects to the neurosynaptic system via the interconnect.

公开(公告)号：US10650301B2

公开(公告)日：2020-05-12

申请号：US14273487

申请日：2014-05-08

申请人： International Business Machines Corporation

发明人： Rodrigo Alvarez-Icaza Rivera ,  Rathinakumar Appuswamy ,  John V. Arthur ,  Andrew S. Cassidy ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada

IPC分类号： G06N3/04 ,  G06N3/063

摘要： Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons.

公开(公告)号：US10454759B2

公开(公告)日：2019-10-22

申请号：US15950037

申请日：2018-04-10

申请人： International Business Machines Corporation

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada

IPC分类号： G06F11/00 ,  G06N3/04 ,  G06N3/063 ,  G06F11/07 ,  H04L12/24

摘要： Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.

公开(公告)号：US10204118B2

公开(公告)日：2019-02-12

申请号：US15197599

申请日：2016-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Pallab Datta ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06F17/30 ,  G06N3/04 ,  G06N3/063 ,  G06F17/10 ,  G06N3/08

摘要： Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table.

公开(公告)号：US10169700B2

公开(公告)日：2019-01-01

申请号：US15362948

申请日：2016-11-29

申请人： International Business Machines Corporation

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06N3/04 ,  G06N3/063

摘要： Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.

公开(公告)号：US20180082174A1

公开(公告)日：2018-03-22

申请号：US15812616

申请日：2017-11-14

申请人： International Business Machines Corporation

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Steven K. Esser ,  Myron D. Flickner ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada ,  Benjamin G. Shaw

IPC分类号： G06N3/06

CPC分类号： G06N3/06

摘要： One embodiment of the invention provides a system comprising at least one spike-to-data converter unit for converting spike event data generated by neurons to output numeric data. Each spike-to-data converter unit is configured to support one or more spike codes.

公开(公告)号：US20160321539A1

公开(公告)日：2016-11-03

申请号：US14229756

申请日：2014-03-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Bryan L. Jackson ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Jun Sawada

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/049

摘要： The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.

摘要翻译： 本发明提供一种包括多个核心电路的系统。 每个核心电路包括用于接收事件分组的多个电子轴突，用于生成事件分组的多个电子神经元和包括用于将神经元与轴突互连的多个电子突触装置的扇出交叉开关。 该系统还包括用于在核心电路之间路由事件分组的路由系统。 路由系统通过将由神经元产生的每个事件分组路由到目标轴突来虚拟地将每个神经元与用于神经元的一个或多个可编程目标轴突连接。 每个核心电路的每个神经元的每个目标轴突是位于与神经元相同的核心电路或与神经元不同的核心电路的轴突。

公开(公告)号：US09160617B2

公开(公告)日：2015-10-13

申请号：US13631544

申请日：2012-09-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  John E. Barth, Jr. ,  Andrew S. Cassidy ,  Subramanian Iyer ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06F15/16 ,  H04L12/24 ,  G06F15/80 ,  H04L12/933 ,  H04L12/939

CPC分类号： G06F11/2033 ,  G06F11/165 ,  G06F15/803 ,  G06F2201/845 ,  H04L41/0654 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/552 ,  H04L49/557

摘要： Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.

摘要翻译： 本发明的实施例涉及处理器阵列上的三维（3-D）网络的故障恢复机制。 一个实施例包括用于处理器阵列的多维交换机网络。 交换机网络包括用于在处理器阵列的多个核心电路之间路由分组的多个交换机。 开关被组织成多个平面。 开关网络还包括包括多个冗余开关的冗余平面。 多个数据路径互连交换机。 在发生一个或多个组件故障的情况下，冗余平面用于促进处理器阵列的完全操作。

公开(公告)号：US20140180985A1

公开(公告)日：2014-06-26

申请号：US13725442

申请日：2012-12-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Paliab Datta ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06N3/02

CPC分类号： G06F17/30292 ,  G06F17/10 ,  G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

摘要： Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table.

摘要翻译： 本发明的实施例涉及将神经模型的神经动力学映射到查找表。 一个实施例包括定义用于神经模型的相平面。 相位平面代表神经模型的神经动力学。 相平面被粗略采样以获得多个神经元状态的状态转换信息。 状态转换信息映射到查找表。

公开(公告)号：US20140095923A1

公开(公告)日：2014-04-03

申请号：US13631496

申请日：2012-09-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  John E. Barth, JR. ,  Andrew S. Cassidy ,  Subramanian Iyer ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06F11/20

CPC分类号： H04L49/1523 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/2041 ,  G06F11/2051 ,  H04L45/28 ,  H04L49/109 ,  H04L49/557

摘要： Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array.

摘要翻译： 本发明的实施例涉及处理器阵列上的二维（2-D）网络的故障恢复机制。 一个实施例包括包括多个处理器核心电路的处理器阵列和用于在核心电路之间路由分组的冗余路由系统。 冗余路由系统包括多个交换机，其中每个交换机对应于处理器阵列的一个或多个核心电路。 冗余路由系统还包括互连交换机的多个数据路径，以及用于选择一个或多个数据路径的控制器。 每个选择的数据路径用于绕过处理器阵列的至少一个组件故障，以便于处理器阵列的完全操作。