公开(公告)号：US20250113546A1

公开(公告)日：2025-04-03

申请号：US18897024

申请日：2024-09-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Takeshi SAKAI ,  Akihiro HANADA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.

公开(公告)号：US20250113544A1

公开(公告)日：2025-04-03

申请号：US18895591

申请日：2024-09-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device according to an embodiment of the present invention includes: an oxide semiconductor layer; a first gate electrode facing the oxide semiconductor layer; a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; an electrode arranged in a region overlapping the oxide semiconductor layer in a plan view and electrically connected to the oxide semiconductor layer; and a metal nitride layer between the oxide semiconductor layer and the electrode, wherein the oxide semiconductor layer is polycrystalline, and an etching rate of the oxide semiconductor layer with respect to an etchant containing phosphoric acid as a main component is less than 3 nm/min at 40° C.

公开(公告)号：US20250113535A1

公开(公告)日：2025-04-03

申请号：US18895467

申请日：2024-09-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Masahiro WATABE

IPC: H01L29/786

Abstract: A semiconductor device includes a light shielding layer, a first silicon nitride insulating layer in contact with the light shielding layer with a first interface, a first silicon oxide insulating layer in contact with the first silicon nitride layer with a second interface, and an oxide semiconductor layer over the first silicon oxide insulating layer. The first silicon oxide insulating layer is in contact with the second silicon oxide insulating layer. A thickness t of the first silicon nitride layer satisfies a condition in which light reflected at the first interface and light reflected at the second interface weaken each other when light having a wavelength of 450 nm is incident on the first silicon nitride insulating layer at an angle of 60 degrees from a normal direction of the second interface.

公开(公告)号：US20250081617A1

公开(公告)日：2025-03-06

申请号：US18817366

申请日：2024-08-28

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Akihiro HANADA ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Masahiro WATABE

IPC: H01L27/12 ,  G02F1/1368

Abstract: A display device having a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels includes, a transistor including an oxide semiconductor layer, a gate wiring extending in the first direction opposite the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring, a first conductive layer provided on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer, a second insulating layer provided on the first conductive layer, a first inorganic layer provided on the second insulating layer and having openings therein, and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening.

公开(公告)号：US20250081540A1

公开(公告)日：2025-03-06

申请号：US18950230

申请日：2024-11-18

Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/06 ,  H01L29/49

Abstract: A thin film transistor includes an oxide semiconductor layer having a polycrystalline structure over a substrate, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first carrier concentration and overlapping the gate electrode, a second region having a second carrier concentration and not overlapping the gate electrode, and a third region between the first region and the second region and overlapping the gate electrode. The second carrier concentration is larger than the first carrier concentration. A carrier concentration of the third region decreases from the second region to the first region in a channel length direction. A length of the third region is greater than or equal to 0.00 μm and less than or equal to 0.60 μm in the channel length direction.

公开(公告)号：US20250063751A1

公开(公告)日：2025-02-20

申请号：US18934519

申请日：2024-11-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/66 ,  H01L21/02

Abstract: A method for manufacturing a semiconductor device comprises steps of: forming an oxide semiconductor layer on a substrate by a sputtering method; performing a first heat treatment on the oxide semiconductor layer after placing the substrate on which the oxide semiconductor layer is formed in a heating furnace having a heating medium maintained at a preset temperature; forming a gate insulating layer on the oxide semiconductor layer after the first heat treatment; and forming a gate electrode on the gate insulating layer. When the substrate is installed in the heating furnace, a temperature drop of the heating medium is kept within 15% of the set temperature.

公开(公告)号：US20250022966A1

公开(公告)日：2025-01-16

申请号：US18898831

申请日：2024-09-27

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a metal oxide layer over an insulating surface and an oxide semiconductor layer over the metal oxide layer. A fluorine concentration of the metal oxide semiconductor layer is greater than or equal to 1×1018 atoms/cm3. In a SIMS analysis, a secondary ion intensity of fluorine detected in the metal oxide layer may be greater than or equal to 10 times a secondary ion intensity of fluorine detected in the oxide semiconductor layer.

公开(公告)号：US20250015196A1

公开(公告)日：2025-01-09

申请号：US18889394

申请日：2024-09-19

Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

IPC: H01L29/786 ,  H01L29/66

Abstract: A thin film transistor includes a metal oxide layer over the substrate, an oxide semiconductor layer having crystallinity in contact with the metal oxide layer, a gate electrode overlapping the oxide semiconductor layer, and an insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation , a crystal orientation , and a crystal orientation obtained by an EBSD method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation is less than or equal to 5%.

公开(公告)号：US20250015189A1

公开(公告)日：2025-01-09

申请号：US18894346

申请日：2024-09-24

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/66 ,  H10K59/121

Abstract: A semiconductor device includes a metal oxide layer over an insulating surface, an oxide semiconductor layer over the metal oxide layer, and an insulating layer over the oxide semiconductor. The insulating layer includes a first region overlapping the oxide semiconductor layer. A first aluminum concentration of the first region is greater than or equal to 1×1017 atoms/cm3.

公开(公告)号：US20250006783A1

公开(公告)日：2025-01-02

申请号：US18830651

申请日：2024-09-11

Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

IPC: H01L29/04 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

Abstract: A thin film transistor includes an oxide semiconductor layer having crystallinity over a substrate, a gate electrode overlapping the oxide semiconductor layer, and an insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation , a crystal orientation , and a crystal orientation obtained by an EBSD method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation is greater than an occupancy rate of the crystal orientation and an occupancy rate of the crystal orientation .