公开(公告)号：US20240379829A1

公开(公告)日：2024-11-14

申请号：US18656855

申请日：2024-05-07

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/66 ,  G02F1/1368 ,  H01L29/45 ,  H01L29/786 ,  H10K59/122

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a thickness of the first region and a thickness of the second region is less than or equal to 1 nm.

公开(公告)号：US20240379865A1

公开(公告)日：2024-11-14

申请号：US18651909

申请日：2024-05-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/417

Abstract: A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.

公开(公告)号：US20240332427A1

公开(公告)日：2024-10-03

申请号：US18604840

申请日：2024-03-14

Applicant: Japan Display Inc.

Inventor： Marina MOCHIZUKI ,  Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/6675

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.

公开(公告)号：US20250022964A1

公开(公告)日：2025-01-16

申请号：US18760532

申请日：2024-07-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423

Abstract: A semiconductor device comprises a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a gate wiring on the gate insulating layer, and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. The first region overlaps the gate insulating layer and the gate wiring. The third region is in contact with the second insulating layer. A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer.

公开(公告)号：US20240194795A1

公开(公告)日：2024-06-13

申请号：US18438564

申请日：2024-02-12

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L27/12 ,  H01L29/423 ,  H10K59/121

CPC classification number: H01L29/78696 ,  H01L21/02164 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/7869 ,  G02F1/134363 ,  G02F1/1368 ,  G02F1/13685 ,  H10K59/1213

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20210367082A1

公开(公告)日：2021-11-25

申请号：US17393452

申请日：2021-08-04

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L29/423

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20240332429A1

公开(公告)日：2024-10-03

申请号：US18618022

申请日：2024-03-27

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device comprises a metal oxide layer on an insulating surface; an oxide semiconductor layer on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; and a gate wiring on the gate insulating layer. The metal oxide layer has a first region overlapping the gate wiring and the oxide semiconductor layer, a second region overlapping the oxide semiconductor layer and not overlapping the gate wiring, and a third region overlapping the gate wiring and not overlapping the oxide semiconductor layer.

公开(公告)号：US20240332308A1

公开(公告)日：2024-10-03

申请号：US18597186

申请日：2024-03-06

Applicant: Japan Display Inc.

Inventor： Marina MOCHIZUKI ,  Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L27/1225 ,  G02F1/1368 ,  H01L27/1274 ,  H01L29/7869 ,  H10K59/1213

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer. The interlayer insulating layer covers the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a film thickness of the first region and a film thickness of the second region is less than or equal to 5 nm.

公开(公告)号：US20240250091A1

公开(公告)日：2024-07-25

申请号：US18411028

申请日：2024-01-12

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/7869 ,  G02F1/1368

Abstract: A semiconductor device includes an oxide semiconductor layer including a polycrystalline structure, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer connected to the oxide semiconductor layer, and a second transparent conductive layer arranged in the same layer as the first transparent conductive layer and separated from the first transparent conductive layer, wherein crystallizability of the first transparent conductive layer is different from crystallizability of the second transparent conductive layer.

公开(公告)号：US20250081617A1

公开(公告)日：2025-03-06

申请号：US18817366

申请日：2024-08-28

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Akihiro HANADA ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Masahiro WATABE

IPC: H01L27/12 ,  G02F1/1368

Abstract: A display device having a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels includes, a transistor including an oxide semiconductor layer, a gate wiring extending in the first direction opposite the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring, a first conductive layer provided on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer, a second insulating layer provided on the first conductive layer, a first inorganic layer provided on the second insulating layer and having openings therein, and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening.