公开(公告)号：US06286094B1

公开(公告)日：2001-09-04

申请号：US09263663

申请日：1999-03-05

申请人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le ,  Brian R. Konigsburg

发明人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le ,  Brian R. Konigsburg

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.

摘要翻译： 公开了一种用于确定处理系统中是否需要调度槽的方法和系统。 所述方法和系统包括多个预解码比特，以提供路由信息并利用所述预解码比特来允许指令被引导到特定解码时隙，并且在不检查指令的情况下服从调度约束。 该预编码系统方案的目的是为了提供关于指令分组的可能性最大的信息，而不增加使用该信息进行解码和组形成的逻辑的复杂性。 在优选实施例中，分析可以并行发出的每个指令的预解码位，并且为指令流内的每个可能的起始位置保留多路复用器控制。

公开(公告)号：US5963723A

公开(公告)日：1999-10-05

申请号：US827076

申请日：1997-03-26

申请人： Hung Qui Le

发明人： Hung Qui Le

IPC分类号： G06F9/38

CPC分类号： G06F9/3853 ,  G06F9/3885

摘要： In a superscalar data processing system, instructions, which are dependent upon each other, are paired for dispatch to a plurality of execution units. Pairing results in instructions being paired that may not necessarily be located at contiguous addresses. Pairing may be performed by comparing general purpose register source pointers and general purpose register target pointers of the various instructions. Pairing may also be accomplished by comparing target identification numbers of source operands with target identification numbers of target instructions.

摘要翻译： 在超标量数据处理系统中，依赖于彼此的指令被配对用于调度到多个执行单元。 配对导致配对的指令可能不一定位于连续的地址。 可以通过比较各种指令的通用寄存器源指针和通用寄存器目标指针来执行配对。 配对也可以通过将源操作数的目标识别号与目标指令的目标识别号进行比较来实现。

公开(公告)号：US5870582A

公开(公告)日：1999-02-09

申请号：US829671

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3863

摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.

摘要翻译： 在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。 处理器资源被窥探以获得标记指令的执行结果。 响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。 响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。 重命名缓冲器可以包括历史缓冲器。 此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。 此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。 因此，在这样的组中可能存在许多不可中断的指令。 这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。 响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

公开(公告)号：US5864341A

公开(公告)日：1999-01-26

申请号：US761875

申请日：1996-12-06

申请人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3891 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.

摘要翻译： 本发明涉及一种用于在信息处理系统中调度指令的方法和装置。 预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。 执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个 第一执行单元转发第一个结果后的结果。 本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。

公开(公告)号：US5841999A

公开(公告)日：1998-11-24

申请号：US633327

申请日：1996-04-17

申请人： Hung Qui Le ,  Erdem Hokenek

发明人： Hung Qui Le ,  Erdem Hokenek

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An information handling system includes an instruction unit, one or more execution units, a memory management unit, connected to the instruction unit, to a memory system, a cache management unit, one or more levels of cache memory associated with the one or more execution units, one or more I/O controllers connected to a bus which connects to the execution units and to the memory systems and to cache, and a completion unit for tracking sequence of instruction dispatch and instruction completion. The completion unit includes a Content Addressable Register Buffer Assignment Table, a Register Status Table, an Instruction Queue, and a Completion Table to control order of execution and completion of instructions in a sequence dependent on availability of operands.

摘要翻译： 信息处理系统包括指令单元，一个或多个执行单元，连接到指令单元的存储器管理单元，存储器系统，高速缓存管理单元，与一个或多个执行相关联的一个或多个高速缓冲存储器级 连接到连接到执行单元和存储器系统的总线的一个或多个I / O控制器和缓存，以及用于跟踪指令分派和指令完成的顺序的完成单元。 完成单元包括内容可寻址寄存器缓冲器分配表，寄存器状态表，指令队列和完成表，以根据操作数的可用性来控制顺序执行和完成指令。

公开(公告)号：US5805906A

公开(公告)日：1998-09-08

申请号：US729308

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  Paul Joseph Jordan

发明人： Hoichi Cheong ,  Hung Qui Le ,  Paul Joseph Jordan

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3855 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to processor registers, information ("results") resulting from and associated with executing instructions. Certain of the results are stored for restoring to the registers. In response to an interruption at least one of the ports is accessed for restoring stored results to the registers. Accesses to the ports are arbitrated in response to comparing writeback and restoration results. A result includes identification of the instruction the result is associated with (a "TID"), and a register that is targeted by the result (a "TR"). The comparing includes comparing TID's and TR's for the results.

摘要翻译： 在使用多个用于处理指令的寄存器的数据处理系统中，用于将信息写入寄存器的方法和装置。 访问端口以写回处理器寄存器，由执行指令产生并与执行指令相关联的信息（“结果”）。 某些结果存储用于恢复到寄存器。 响应于中断，访问至少一个端口以将存储的结果恢复到寄存器。 响应于回写和恢复结果的比较，对端口的访问进行仲裁。 结果包括与结果相关联的指令的识别（“TID”）和由结果（“TR”）定向的寄存器。 比较包括比较TID和TR的结果。

公开(公告)号：US08521998B2

公开(公告)日：2013-08-27

申请号：US12793718

申请日：2010-06-04

申请人： Christopher Michael Abernathy ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt

发明人： Christopher Michael Abernathy ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt

IPC分类号： G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30 ,  G06F9/3851 ,  G06F9/3857

摘要： A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.

摘要翻译： 一种用于跟踪处理器中的指令的方法和装置。 处理器中的完成单元接收到添加到表中以形成接收到的指令组的指令组。 响应于接收到接收到的指令组，完成单元确定是否存在包含在第一位置中的先前存储的指令组的条目，并且具有用于存储接收到的指令组的空间。 响应于存在的条目，完成单元将接收到的指令组存储在条目中的第二位置，以形成存储的指令组。

公开(公告)号：US07594096B2

公开(公告)日：2009-09-22

申请号：US11950495

申请日：2007-12-05

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3851

摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.

摘要翻译： 本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。 这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。 可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将 进入处理器，导致执行时间缩短。 当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。 在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。 一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。 两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。 如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

公开(公告)号：US07444498B2

公开(公告)日：2008-10-28

申请号：US11016236

申请日：2004-12-17

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F7/00

CPC分类号： G06F9/3842 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3851

摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.

摘要翻译： 本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。 这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。 可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将 进入处理器，导致执行时间缩短。 当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。 在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。 一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。 两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。 如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

公开(公告)号：US20080250230A1

公开(公告)日：2008-10-09

申请号：US12061290

申请日：2008-04-02

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838

摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.

摘要翻译： 本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。 这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。 这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。 以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如 通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。 在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。 跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。 改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。 修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。 当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。 否则，将使用来自架构化寄存器的数据。