公开(公告)号：US5805906A

公开(公告)日：1998-09-08

申请号：US729308

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  Paul Joseph Jordan

发明人： Hoichi Cheong ,  Hung Qui Le ,  Paul Joseph Jordan

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3855 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to processor registers, information ("results") resulting from and associated with executing instructions. Certain of the results are stored for restoring to the registers. In response to an interruption at least one of the ports is accessed for restoring stored results to the registers. Accesses to the ports are arbitrated in response to comparing writeback and restoration results. A result includes identification of the instruction the result is associated with (a "TID"), and a register that is targeted by the result (a "TR"). The comparing includes comparing TID's and TR's for the results.

摘要翻译： 在使用多个用于处理指令的寄存器的数据处理系统中，用于将信息写入寄存器的方法和装置。 访问端口以写回处理器寄存器，由执行指令产生并与执行指令相关联的信息（“结果”）。 某些结果存储用于恢复到寄存器。 响应于中断，访问至少一个端口以将存储的结果恢复到寄存器。 响应于回写和恢复结果的比较，对端口的访问进行仲裁。 结果包括与结果相关联的指令的识别（“TID”）和由结果（“TR”）定向的寄存器。 比较包括比较TID和TR的结果。

公开(公告)号：US6061777A

公开(公告)日：2000-05-09

申请号：US959646

申请日：1997-10-28

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le ,  Soummya Mallick

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le ,  Soummya Mallick

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3863 ,  G06F9/384

摘要： One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

摘要翻译： 本发明的一个方面涉及一种用于操作处理器的方法。 在本发明的一个版本中，该方法包括发送指令的步骤; 确定由发送的指令所针对的架构寄存器的目前架构化的RMAP条目; 选择与包含调度指令的操作数的物理寄存器相关联的RMAP条目; 更新所选RMAP条目中的使用指示符; 确定发送的指令是否可中断; 以及如果所分派的指令是不间断的，则更新当前架构的RMAP条目中的架构指示符和历史指示符。

公开(公告)号：US5983341A

公开(公告)日：1999-11-09

申请号：US840921

申请日：1997-04-25

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F9/06 ,  G06F9/22

CPC分类号： G06F9/3836 ,  G06F9/3855

摘要： A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.

摘要翻译： 数据处理系统指示由于缓存未命中或由于非高速缓存未命中延迟而导致指令没有可用数据。 当指令不能访问可用数据并且高速缓存未命中时，不发出取决于发出的指令的指令。 然而，如果由于非高速缓存未命中延迟而导致负载执行被延迟，那么取决于所发出的指令的指令也是在下一个定时周期中预期成功的加载指令执行的情况下发出的。 通过使用这种发布机制，随着执行单元更好地利用其管道，数据处理系统的效率得到提高。

公开(公告)号：US5875326A

公开(公告)日：1999-02-23

申请号：US840919

申请日：1997-04-25

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857

摘要： During operation of a pipelined data processing system, an interruptible instruction table is used to store target identifiers associated with instructions which may result in speculative execution. During operation of the interruptible instruction table, a pointer, referred to as a completing instruction buffer entry pointer, points to a bottom of the interruptible instruction table if that table includes any instruction. An entry at the bottom of the interruptible instruction table is a next instruction to complete. This entry includes a target identifier, referred to as a non-speculative-non-interruptible TID, may be used to release resources held for all prior executed instructions. The data processing system determines the value of the non-speculative-non-interruptible TID to ensure that order determination is preserved and provides a true speculative execution point.

摘要翻译： 在流水线数据处理系统的操作期间，可中断指令表用于存储与可能导致推测执行的指令相关联的目标标识符。 在可中断指令表的操作期间，如果该表包括任何指令，则称为完成指令缓冲器入口指针的指针指向可中断指令表的底部。 可中断指令表底部的条目是要完成的下一条指令。 该条目包括被称为不推测不可中断的TID的目标标识符可用于释放为所有先前执行的指令保持的资源。 数据处理系统确定非推测不可中断TID的值，以确保顺序确定被保留并提供真实的推测执行点。

公开(公告)号：US5974524A

公开(公告)日：1999-10-26

申请号：US959647

申请日：1997-10-28

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Quan Nguyen ,  Hung Qui Le

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Quan Nguyen ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/384 ,  G06F9/3857 ,  G06F9/3863

摘要： According to one aspect of the invention, a method is provided for maintaining the state of a processor having a plurality of physical registers and a rename register map which stores rename pairs that associate architected and physical registers, the rename register map having a plurality of entries which are associated with the physical registers, individual entries having an architected register field, an architected status bit and a history status bit. In one version, the method includes the steps of dispatching an instruction which targets an architected register; determining a presently architected entry in the rename register map in which an architected pointer in the architected register field of the entry matches the architected register pointer of the architected register targeted by the dispatched instruction and the architected status bit is set; resetting the architected status bit; setting the history status bit in the entry and saving the physical register pointer to a checkpoint recovery table if the dispatched instruction is interruptible or if the architected register of the dispatched instruction has not been targeted since the latest dispatched interruptible instruction; determining a next available rename register map entry; writing a pointer to the architected register targeted by the instruction into the architected register field and setting the architected status bit in the next available rename register map entry.

摘要翻译： 根据本发明的一个方面，提供了一种用于维护具有多个物理寄存器的处理器的状态和存储重新命名对的重命名寄存器映射的方法，所述重命名对将结构化和物理寄存器相关联，重命名寄存器映射具有多个条目 其与物理寄存器相关联，具有架构化寄存器字段的单个条目，架构状态位和历史状态位。 在一个版本中，该方法包括调度针对架构化寄存器的指令的步骤; 确定重命名寄存器映射中的目前架构的条目，其中该条目的架构化寄存器字段中的架构指针与被调度指令所针对的架构化寄存器的架构化寄存器指针相匹配并且构建状态位被设置; 重置架构状态位; 如果发送的指令是可中断的，或者如果从最近发出的可中断指令起未指定调度指令的架构寄存器，则将条目的历史状态位设置为条目，并将物理寄存器指针保存到检查点恢复表; 确定下一个可用的重命名寄存器映射条目; 将指针写入到由架构寄存器字段指定的架构寄存器的指针，并将下一个可用重命名寄存器映射条目中的架构状态位置1。

公开(公告)号：US5870582A

公开(公告)日：1999-02-09

申请号：US829671

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3863

摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.

摘要翻译： 在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。 处理器资源被窥探以获得标记指令的执行结果。 响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。 响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。 重命名缓冲器可以包括历史缓冲器。 此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。 此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。 因此，在这样的组中可能存在许多不可中断的指令。 这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。 响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

公开(公告)号：US5822752A

公开(公告)日：1998-10-13

申请号：US680745

申请日：1996-07-15

申请人： Hoichi Cheong ,  Michael Kevin Ciraula ,  Hung Qui Le ,  John Stephen Muhich

发明人： Hoichi Cheong ,  Michael Kevin Ciraula ,  Hung Qui Le ,  John Stephen Muhich

IPC分类号： G06F12/02 ,  G06F7/78 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F7/785

摘要： The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.

摘要翻译： 本发明涉及一种用于管理具有多个队列条目的随机顺序队列的电路，每个队列条目具有指示队列条目是否包含有效数据的相关联的有效位。 在一个实施例中，电路包括用于响应于第一组有效位的接收有效信号的第一多个输入端，用于响应于第二组有效位而接收移位信号的第二多个输入端，以及用于提供 选择耦合到队列的复用器的信号，所述选择信号响应于移位信号和有效信号。

公开(公告)号：US06535973B1

公开(公告)日：2003-03-18

申请号：US09383606

申请日：1999-08-26

申请人： Hoichi Cheong ,  Maureen A. Delaney ,  Hung Qui Le ,  Robert McDonald ,  Dung Quoc Nguyen ,  David Wayne Victor

发明人： Hoichi Cheong ,  Maureen A. Delaney ,  Hung Qui Le ,  Robert McDonald ,  Dung Quoc Nguyen ,  David Wayne Victor

IPC分类号： G06F9312

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are issued after execution of the primary instruction. N clock cycles are tracked after execution of the primary instruction, wherein the result from execution of said primary instruction is expected within n clock cycles. Execution of any speculatively issued instructions which are dependent upon the primary instruction is cancelled if the result is not returned from execution of the primary instruction within n clock cycles, such that for primary instructions for which the result is returned within the expected n clock cycles any speculatively issued instructions dependent upon said result are executed with increased efficiency.

摘要翻译： 用于推测发出指令的方法和系统，其依赖于执行其他指令的结果。 根据执行主指令的结果推测发出指令，其中在执行主指令之后发出推测发出的指令。 在执行主指令之后追踪N个时钟周期，其中预期在n个时钟周期内执行所述主指令的结果。 如果在n个时钟周期内没有从主指令的执行中返回结果，则取消依赖于主指令的任何推测发出的指令的执行，使得对于在预期的n个时钟周期内返回结果的主指令， 推测发出依赖于所述结果的指令以更高的效率执行。

公开(公告)号：US6070235A

公开(公告)日：2000-05-30

申请号：US892589

申请日：1997-07-14

申请人： Hoichi Cheong ,  Hung Qui Le

发明人： Hoichi Cheong ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A data processing system includes logic to ensure result data stored in a history buffer is in a correct chronological order and is not overwritten until an appropriate point in time. The logic also ensures that the history buffer is able to capture result data that is produced with unexpected delays. The history buffer entries act as a "backup" for an architected register by storing older result data and rely on unique target identifiers assigned to dispatched instructions to keep the result data in a correct chronological order. Furthermore, a target identifier field of the architected register holds the latest target identifier assigned to a youngest instruction that modifies the architected register. Additionally, previous result data in the register is backed up in an allocated history buffer entry. If the result data is not yet available, the target identifier in the register will be deposited in the target identifier field of the history buffer entry. One timing cycle before a result data value is expected to be available, a target identifier assigned to the instruction producing the data is broadcast on the Result bus. If the result data is delayed at a next timing cycle, a re-execute signal is asserted on the Result bus to notify a history buffer entry or a register that the data is not ready to be stored therein. Furthermore, the re-execute signal remains asserted until the result data is available. During the same cycle, the re-execute signal is negated, result data is presented on the Result bus. A functional unit that broadcasts an asserted re-execute signal after it broadcasts a first target identifier, can broadcast a second target identifer before the re-execute signal is negated.

摘要翻译： 数据处理系统包括用于确保存储在历史缓冲器中的结果数据具有正确的时间顺序并且不被覆盖直到适当的时间点的逻辑。 该逻辑还可确保历史缓冲区能够捕获由意外延迟产生的结果数据。 历史缓冲区条目通过存储较旧的结果数据作为架构化寄存器的“备份”，并依赖分配给调度指令的唯一目标标识符来保持结果数据的正确时间顺序。 此外，架构化寄存器的目标标识符字段保存分配给修改架构化寄存器的最年轻指令的最新目标标识符。 此外，寄存器中的先前结果数据将在已分配的历史缓冲区条目中进行备份。 如果结果数据不可用，则寄存器中的目标标识符将被存入历史缓冲区条目的目标标识符字段中。 在结果数据值预期可用之前的一个定时周期，分配给产生数据的指令的目标标识符在结果总线上被广播。 如果结果数据在下一个定时周期被延迟，则在结果总线上断言重新执行信号，以将历史缓冲器条目或寄存器通知数据未准备好存储在其中。 此外，重新执行信号保持有效，直到结果数据可用。 在同一周期内，重执行信号被否定，结果数据显示在结果总线上。 在广播第一目标标识符之后广播被断言的重新执行信号的功能单元可以在重新执行信号被否定之前广播第二目标标识符。

公开(公告)号：US5774712A

公开(公告)日：1998-06-30

申请号：US770219

申请日：1996-12-19

申请人： Hoichi Cheong ,  Hung Qui Le

发明人： Hoichi Cheong ,  Hung Qui Le

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3855 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3889

摘要： The present invention is directed to an apparatus and method for sending and receiving instructions, or operations, in an information handling system. The operations are received in a particular, desired order, regardless of the order in which the operations are sent. The invention provides an apparatus and method which assigns a vector to each operation or sub-operation to indicate the desired receiving order of the operations. In addition, the apparatus and method implementing the invention assign a vector to the receiving unit to indicate the order into which the operations should be placed in the receiving unit. The two vectors are manipulated in such a way as to signal which operations should be accepted into which places in the receiving unit. One operation may be mapped to multiple sub-operations in the receiving unit. In addition, the mapping of the sending order of the opcode portion of the operations and the mapping of the sending order of the data portion of the operation are done in parallel, and thus the mapping does not add cycle time delay to the bus transfer time.

摘要翻译： 本发明涉及一种用于在信息处理系统中发送和接收指令或操作的装置和方法。 以特定的期望顺序接收操作，而不管发送操作的顺序。 本发明提供一种装置和方法，其向每个操作或子操作分配向量以指示操作的期望接收顺序。 此外，实现本发明的装置和方法将向量分配给接收单元，以指示应该在接收单元中放置操作的顺序。 以这样一种方式操纵两个向量，以便将哪个操作应该被接受到接收单元中的哪个位置。 一个操作可以映射到接收单元中的多个子操作。 此外，操作的操作码部分的发送顺序的映射和操作的数据部分的发送顺序的映射是并行完成的，因此映射不会将总线传送时间的周期时间延迟 。