公开(公告)号：US5805906A

公开(公告)日：1998-09-08

申请号：US729308

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  Paul Joseph Jordan

发明人： Hoichi Cheong ,  Hung Qui Le ,  Paul Joseph Jordan

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3855 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to processor registers, information ("results") resulting from and associated with executing instructions. Certain of the results are stored for restoring to the registers. In response to an interruption at least one of the ports is accessed for restoring stored results to the registers. Accesses to the ports are arbitrated in response to comparing writeback and restoration results. A result includes identification of the instruction the result is associated with (a "TID"), and a register that is targeted by the result (a "TR"). The comparing includes comparing TID's and TR's for the results.

摘要翻译： 在使用多个用于处理指令的寄存器的数据处理系统中，用于将信息写入寄存器的方法和装置。 访问端口以写回处理器寄存器，由执行指令产生并与执行指令相关联的信息（“结果”）。 某些结果存储用于恢复到寄存器。 响应于中断，访问至少一个端口以将存储的结果恢复到寄存器。 响应于回写和恢复结果的比较，对端口的访问进行仲裁。 结果包括与结果相关联的指令的识别（“TID”）和由结果（“TR”）定向的寄存器。 比较包括比较TID和TR的结果。

公开(公告)号：US6061777A

公开(公告)日：2000-05-09

申请号：US959646

申请日：1997-10-28

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le ,  Soummya Mallick

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le ,  Soummya Mallick

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3863 ,  G06F9/384

摘要： One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

摘要翻译： 本发明的一个方面涉及一种用于操作处理器的方法。 在本发明的一个版本中，该方法包括发送指令的步骤; 确定由发送的指令所针对的架构寄存器的目前架构化的RMAP条目; 选择与包含调度指令的操作数的物理寄存器相关联的RMAP条目; 更新所选RMAP条目中的使用指示符; 确定发送的指令是否可中断; 以及如果所分派的指令是不间断的，则更新当前架构的RMAP条目中的架构指示符和历史指示符。

公开(公告)号：US5983341A

公开(公告)日：1999-11-09

申请号：US840921

申请日：1997-04-25

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F9/06 ,  G06F9/22

CPC分类号： G06F9/3836 ,  G06F9/3855

摘要： A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.

摘要翻译： 数据处理系统指示由于缓存未命中或由于非高速缓存未命中延迟而导致指令没有可用数据。 当指令不能访问可用数据并且高速缓存未命中时，不发出取决于发出的指令的指令。 然而，如果由于非高速缓存未命中延迟而导致负载执行被延迟，那么取决于所发出的指令的指令也是在下一个定时周期中预期成功的加载指令执行的情况下发出的。 通过使用这种发布机制，随着执行单元更好地利用其管道，数据处理系统的效率得到提高。

公开(公告)号：US5875326A

公开(公告)日：1999-02-23

申请号：US840919

申请日：1997-04-25

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857

摘要： During operation of a pipelined data processing system, an interruptible instruction table is used to store target identifiers associated with instructions which may result in speculative execution. During operation of the interruptible instruction table, a pointer, referred to as a completing instruction buffer entry pointer, points to a bottom of the interruptible instruction table if that table includes any instruction. An entry at the bottom of the interruptible instruction table is a next instruction to complete. This entry includes a target identifier, referred to as a non-speculative-non-interruptible TID, may be used to release resources held for all prior executed instructions. The data processing system determines the value of the non-speculative-non-interruptible TID to ensure that order determination is preserved and provides a true speculative execution point.

摘要翻译： 在流水线数据处理系统的操作期间，可中断指令表用于存储与可能导致推测执行的指令相关联的目标标识符。 在可中断指令表的操作期间，如果该表包括任何指令，则称为完成指令缓冲器入口指针的指针指向可中断指令表的底部。 可中断指令表底部的条目是要完成的下一条指令。 该条目包括被称为不推测不可中断的TID的目标标识符可用于释放为所有先前执行的指令保持的资源。 数据处理系统确定非推测不可中断TID的值，以确保顺序确定被保留并提供真实的推测执行点。

公开(公告)号：US5974524A

公开(公告)日：1999-10-26

申请号：US959647

申请日：1997-10-28

申请人： Hoichi Cheong ,  Paul Joseph Jordan ,  Quan Nguyen ,  Hung Qui Le

发明人： Hoichi Cheong ,  Paul Joseph Jordan ,  Quan Nguyen ,  Hung Qui Le

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/384 ,  G06F9/3857 ,  G06F9/3863

摘要： According to one aspect of the invention, a method is provided for maintaining the state of a processor having a plurality of physical registers and a rename register map which stores rename pairs that associate architected and physical registers, the rename register map having a plurality of entries which are associated with the physical registers, individual entries having an architected register field, an architected status bit and a history status bit. In one version, the method includes the steps of dispatching an instruction which targets an architected register; determining a presently architected entry in the rename register map in which an architected pointer in the architected register field of the entry matches the architected register pointer of the architected register targeted by the dispatched instruction and the architected status bit is set; resetting the architected status bit; setting the history status bit in the entry and saving the physical register pointer to a checkpoint recovery table if the dispatched instruction is interruptible or if the architected register of the dispatched instruction has not been targeted since the latest dispatched interruptible instruction; determining a next available rename register map entry; writing a pointer to the architected register targeted by the instruction into the architected register field and setting the architected status bit in the next available rename register map entry.

摘要翻译： 根据本发明的一个方面，提供了一种用于维护具有多个物理寄存器的处理器的状态和存储重新命名对的重命名寄存器映射的方法，所述重命名对将结构化和物理寄存器相关联，重命名寄存器映射具有多个条目 其与物理寄存器相关联，具有架构化寄存器字段的单个条目，架构状态位和历史状态位。 在一个版本中，该方法包括调度针对架构化寄存器的指令的步骤; 确定重命名寄存器映射中的目前架构的条目，其中该条目的架构化寄存器字段中的架构指针与被调度指令所针对的架构化寄存器的架构化寄存器指针相匹配并且构建状态位被设置; 重置架构状态位; 如果发送的指令是可中断的，或者如果从最近发出的可中断指令起未指定调度指令的架构寄存器，则将条目的历史状态位设置为条目，并将物理寄存器指针保存到检查点恢复表; 确定下一个可用的重命名寄存器映射条目; 将指针写入到由架构寄存器字段指定的架构寄存器的指针，并将下一个可用重命名寄存器映射条目中的架构状态位置1。

公开(公告)号：US06658534B1

公开(公告)日：2003-12-02

申请号：US09052247

申请日：1998-03-31

申请人： Steven Wayne White ,  Hung Qui Le ,  Kurt Alan Feiste ,  Paul Joseph Jordan

发明人： Steven Wayne White ,  Hung Qui Le ,  Kurt Alan Feiste ,  Paul Joseph Jordan

IPC分类号： G06F1200

CPC分类号： G06F9/382 ,  G06F9/3804 ,  G06F12/0862

摘要： The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.

摘要翻译： 实现了通过启动早期高速缓存行预取来减少指令高速缓存未达错误的机制。 该机制在提取期间检测到指令高速缓存未命中导致指令高速缓存未命中之前提供对下一个后续高速缓存行的早期预取。 当保证将引用后续高速缓存行中的指令时，启动预取。 当当前指令是非分支指令时，会发生这种情况，因此指令将顺序执行，或者当前指令是分支指令，但分支前进足够短。 如果当前指令是分支，而分支转发到下一个顺序高速缓存行，则可以执行下一个顺序高速缓存行的预取。 以这种方式，可以减少高速缓存未命中延迟，而不会由于先前未被引用的高速缓存线的预取而产生高速缓存污染。

公开(公告)号：US5805849A

公开(公告)日：1998-09-08

申请号：US829592

申请日：1997-03-31

申请人： Paul Joseph Jordan ,  Brian R. Konigsburg ,  Hung Qui Le ,  Steven Wayne White

发明人： Paul Joseph Jordan ,  Brian R. Konigsburg ,  Hung Qui Le ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857

摘要： A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor. The global signal preconditions portions of the two identifiers being compared. Subsequently, a result of this conditioning is concatenated with a remaining portion of a selected identifier. The modification of the upper bits of the identifier maintains a relative age position for the identifiers and their associated instructions in the pipelined processor.

摘要翻译： 数据处理器为每个指令分配唯一的标识符。 由于存在有限数量的唯一标识符，所以在数据处理系统内的程序执行期间重新使用标识符。 为了保持在流水线处理器中执行的指令之间的年龄关系，开发了一种方法，以确保重复使用的标识符被正确地指定为年龄小于较大的，较大的数量。 为了解决这个问题，假定分配给每个指令的标识符具有N位，因此，有2N个标识符被分配给程序中的指令。 2N个标识符分成2m个银行。 除了为每个指令分配标识符之外，流水线处理器内的标识符分配逻辑电路提供一个全局信号，其指示哪个存储体是最小的存储体，其中标识符从其被分配给流水线处理器的剩余部分。 两个标识符的全局信号前提条件部分被比较。 随后，这种调理的结果与所选标识符的剩余部分连接。 标识符的高位的修改保持流水线处理器中的标识符及其相关联的指令的相对年龄位置。

公开(公告)号：US06629170B1

公开(公告)日：2003-09-30

申请号：US09436110

申请日：1999-11-08

申请人： Joel Roger Davidson ,  Michael Stephen Floyd ,  Paul Joseph Jordan ,  Judith E. K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick

发明人： Joel Roger Davidson ,  Michael Stephen Floyd ,  Paul Joseph Jordan ,  Judith E. K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick

IPC分类号： G06F1300

CPC分类号： G06F11/348 ,  G06F11/349 ,  G06F2201/88

摘要： A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.

摘要翻译： 多级字节通道可选择总线。 在优选实施例中，性能监视模式中的总线包括多个字节通道和选择机构。 选择机制从多个信号中获取希望被监视的那些信号的子集，并将该子集信号放置在输入到PMU的字节通道上。 可能被监视的多个信号的数量大于字节通道的数量，并且也大于PMU计数器的数量。

公开(公告)号：US5999992A

公开(公告)日：1999-12-07

申请号：US542211

申请日：1995-10-12

申请人： Gregory Frederick Grohoski ,  William Rudolph Hardell, Jr. ,  Paul Joseph Jordan ,  Oscar Reid Mitchell ,  Tung Manh Nguyen ,  Yonjae Rim

发明人： Gregory Frederick Grohoski ,  William Rudolph Hardell, Jr. ,  Paul Joseph Jordan ,  Oscar Reid Mitchell ,  Tung Manh Nguyen ,  Yonjae Rim

IPC分类号： G06F13/38 ,  G06F13/14

CPC分类号： G06F13/385

摘要： This invention relates to a system and method for adapting the ports of computing elements in transferring data between computing elements on a network. Ports of the computing elements are interconnected for data transfer through a switch complex. The interconnected ports are adapted to cooperate together in transferring the data. Data which is ordinarily designated to be transferred through one port of a computing element may be transferred through a different port.

摘要翻译： 本发明涉及一种用于使计算元件的端口适配于在网络上的计算元件之间传送数据的系统和方法。 计算元件的端口相互连接，用于通过交换机复杂的数据传输。 互连的端口适于在传送数据时协同工作。 通常被指定为通过计算元件的一个端口传送的数据可以通过不同的端口传送。

公开(公告)号：US06701484B1

公开(公告)日：2004-03-02

申请号：US09635456

申请日：2000-08-11

申请人： Paul Joseph Jordan ,  Peter Juergen Klim

发明人： Paul Joseph Jordan ,  Peter Juergen Klim

IPC分类号： G06F1100

CPC分类号： G06F11/1008 ,  G11C7/22 ,  G11C7/24 ,  G11C2207/2281 ,  G11C2207/229

摘要： A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock cycle. The register has a memory array, and read and write decoders for accessing the memory array using select lines. The select lines are also connected to read and write address latches which are used to index a parity bit array. When a value is written to, or read from, the memory array, its corresponding parity bit is calculated and either stored in the parity bit array (for a write operation), or compared to an existing parity bit array entry (for a read operation). The parity check is performed on a copy of the value contained in a read data latch or a write data latch. Each data latch has an input connected to a respective read or write port of the memory array. The latches delay the parity check by only one cycle.

摘要翻译： 用于计算机处理器的寄存器从CPU操作的关键路径去除奇偶校验，并将奇偶校验延迟到下一个即时时钟周期。 寄存器有一个存储器阵列，以及读和写解码器，用于使用选择行访问存储器阵列。 选择线也连接到用于对奇偶校验位阵列进行索引的读和写地址锁存器。 当将值写入或读取存储器阵列时，其相应的奇偶校验位被计算并存储在奇偶校验位阵列中（用于写操作）或与现有奇偶校验位阵列条目进行比较（对于读操作 ）。 在读数据锁存器或写数据锁存器中包含的值的副本上执行奇偶校验。 每个数据锁存器具有连接到存储器阵列的相应读或写端口的输入。 锁存器将奇偶校验延迟一个周期。