公开(公告)号：US08034699B2

公开(公告)日：2011-10-11

申请号：US12464206

申请日：2009-05-12

申请人： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

发明人： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

IPC分类号： H01L21/425

CPC分类号： H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

摘要： A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

摘要翻译： 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型杂质注入到衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

公开(公告)号：US07732841B2

公开(公告)日：2010-06-08

申请号：US12172309

申请日：2008-07-14

申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC分类号： H01L27/148 ,  H01L31/062

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

摘要翻译： 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US07655966B2

公开(公告)日：2010-02-02

申请号：US12050967

申请日：2008-03-19

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

IPC分类号： H04N3/14

CPC分类号： H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

摘要翻译： 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

公开(公告)号：US07633042B2

公开(公告)日：2009-12-15

申请号：US12172306

申请日：2008-07-14

申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Lolseau

发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Lolseau

IPC分类号： H01L27/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

摘要翻译： 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US20120122261A1

公开(公告)日：2012-05-17

申请号：US13288686

申请日：2011-11-03

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC分类号： H01L31/18

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

摘要： A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

摘要翻译： 一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。 该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。 然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。 去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。 表面注入层形成在具有第一导电类型材料的沟槽的任一侧。 沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

公开(公告)号：US20100097511A1

公开(公告)日：2010-04-22

申请号：US12641589

申请日：2009-12-18

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

IPC分类号： H04N5/335 ,  G06F17/50

CPC分类号： H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

摘要翻译： 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

公开(公告)号：US20080272399A1

公开(公告)日：2008-11-06

申请号：US12172305

申请日：2008-07-14

申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC分类号： H01L31/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

公开(公告)号：US08106432B2

公开(公告)日：2012-01-31

申请号：US12634898

申请日：2009-12-10

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC分类号： H01L31/04

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

摘要翻译： 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间并形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

公开(公告)号：US20120001268A1

公开(公告)日：2012-01-05

申请号：US13228998

申请日：2011-09-09

申请人： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

发明人： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

IPC分类号： H01L27/092

CPC分类号： H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

摘要： A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

摘要翻译： 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型的杂质注入衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

公开(公告)号：US08023021B2

公开(公告)日：2011-09-20

申请号：US12641589

申请日：2009-12-18

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

IPC分类号： H04N5/335

CPC分类号： H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

摘要翻译： 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。