公开(公告)号：US20080123414A1

公开(公告)日：2008-05-29

申请号：US12023317

申请日：2008-01-31

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

摘要翻译： 本发明提供了一种用于感测存储器单元的方案。 所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。 存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。 位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值 到达目前，当前基本上关闭。 特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

公开(公告)号：US07218552B1

公开(公告)日：2007-05-15

申请号：US11223623

申请日：2005-09-09

申请人： Jun Wan ,  Jeffrey W. Lutze

发明人： Jun Wan ,  Jeffrey W. Lutze

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/5648

摘要： A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non-volatile storage elements which are programmed after those associated with the first word line.

摘要翻译： 非易失性存储器被编程为减少对经过增强的抑制存储器元件的编程干扰的发生率以减少编程干扰的方式，但是哪些经验减少了由于其字线位置而引起的益处。 为了实现该结果，调整存储器元件被编程的字线序列，使得较高的字线首先被编程，而不是相对于剩余字线的顺序。 另外，自增强可以用于较高的字线，而擦除区域自增强或变体可用于剩余的字线。 此外，对于在与第一字线相关联的那些之后编程的非易失性存储元件，可以在自增强之前采用禁止的存储器元件的通道的预充电。

公开(公告)号：US07161836B1

公开(公告)日：2007-01-09

申请号：US11194439

申请日：2005-08-01

申请人： Jun Wan ,  Jeffrey W. Lutze

发明人： Jun Wan ,  Jeffrey W. Lutze

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

摘要翻译： 调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。 施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，之后可以将限定的最大数量的附加脉冲施加到其它存储器元件以允许它们也达到相关联的目标阈值电压电平。 该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

公开(公告)号：US07049652B2

公开(公告)日：2006-05-23

申请号：US10732967

申请日：2003-12-10

申请人： Nima Mokhlesi ,  Jeffrey W. Lutze

发明人： Nima Mokhlesi ,  Jeffrey W. Lutze

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

摘要翻译： 柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。 每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。 这个过程的很多方面都是自相矛盾的。 这些存储单元的阵列将需要较少的分割。 此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

公开(公告)号：US08130556B2

公开(公告)日：2012-03-06

申请号：US12398368

申请日：2009-03-05

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

摘要翻译： 编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。 一个方面将交替的相邻位线对组合成第一和第二组。 双编程脉冲被施加到选定的字线。 第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。 然后对所有位线执行验证操作。 当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。 另一个方面分别编写每第三个位线。 修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。

公开(公告)号：US20120014184A1

公开(公告)日：2012-01-19

申请号：US12838902

申请日：2010-07-19

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454 ,  G11C16/3486 ,  G11C2216/14

摘要： Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.

摘要翻译： 使用编程技术使非易失性存储器件中的阈值电压分布变窄，并且/或编程时间减少，其中具有目标数据状态的存储元件的位线电压被升高，在升压锁定步骤中 在编程电压。 根据其目标数据状态，针对存储元件的不同子集，在编程遍历中的不同时刻对位线电压进行升压。 可以基于固定的编程脉冲数或基于编程进度的自适应来设置位线电压中的升压的开始和停止。 变化包括使用固定的位线步长，变化的位线步长，数据状态相关的位线步长，不增加一个或多个数据状态的位线的选项以及增加额外位线偏置的选项。

公开(公告)号：US20110267888A1

公开(公告)日：2011-11-03

申请号：US13181750

申请日：2011-07-13

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并驱动选择栅极电压以精确地控制选择栅极电压以提高写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，与p阱电压一致，在擦除操作期间以特定电平驱动选择栅极。

公开(公告)号：US07876611B2

公开(公告)日：2011-01-25

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻存储元件。

公开(公告)号：US20100238730A1

公开(公告)日：2010-09-23

申请号：US12406014

申请日：2009-03-17

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并且驱动或浮动选择栅极电压以精确地控制选择栅极电压以改善写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，选择门在被特定初始级别驱动之后浮动，以达到特定的最佳最终级别。 在另一种方法中，与p阱电压一致，在擦除操作期间，选择栅极以特定电平驱动。 在另一种方法中，选择栅极浮动的开始被延迟，而p阱电压上升。 在另一种方法中，p阱电压以两个步骤升高，并且在第二个斜坡开始之前，选择栅极不浮动。 可以通过提高驱动电压来切断选通门的通孔来实现浮动。

公开(公告)号：US20100110792A1

公开(公告)日：2010-05-06

申请号：US12398368

申请日：2009-03-05

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

摘要翻译： 编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。 一个方面将交替的相邻位线对组合成第一和第二组。 双编程脉冲被施加到选定的字线。 第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。 然后对所有位线执行验证操作。 当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。 另一个方面分别编写每第三个位线。 修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。