公开(公告)号：US08145986B2

公开(公告)日：2012-03-27

申请号：US12556379

申请日：2009-09-09

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： G06F11/00

CPC分类号： H03M13/116 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6527 ,  H03M13/6544 ,  H03M13/6561

摘要： Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

摘要翻译： 多CSI（循环移位身份）基于子矩阵的LDPC（低密度奇偶校验）码。 使用包括至少一个双值条目并且还可以包括至少一个单值条目和/或至少一个全零值条目的CSI参数集来生成LDPC矩阵。 单值条目中的一个可以是0（用于生成具有循环移位值0的CSI矩阵，对应于身份子矩阵，使得沿着对角线的所有条目具有元素值1，并且其中所有其他元素 是0）。 一旦生成了LDPC矩阵，就采用LDPC编码信号进行解码，对其中编码的信息比特进行估计。 此外，LDPC矩阵本身可以用作LDPC生成器矩阵（或者可替换地，LDPC生成器矩阵可以通过处理LDPC矩阵来生成）用于对信息比特进行编码。

公开(公告)号：US08086930B2

公开(公告)日：2011-12-27

申请号：US12021911

申请日：2008-01-29

申请人： Tak K. Lee ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

发明人： Tak K. Lee ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

IPC分类号： H03M13/11

CPC分类号： H04L1/0043 ,  H04L1/0057 ,  H04L1/009

摘要： Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.

摘要翻译： 用于FEC（前向纠错）码字的固定间隔奇偶校验插入。 当产生码字时，使用固定间隔来分散信息比特之间的奇偶比特。 根据该固定间隔，在码字中的每个奇偶校验位之间放置相同数量的信息比特。 如果需要，奇偶校验位的顺序可以在它们被置入码字之前改变。 此外，信息比特的顺序也可以在它们被置入码字之前被修改。 用于从信息比特生成奇偶校验位的FEC编码可以是各种代码中的任何一种，包括里德 - 所罗门（RS）码，LDPC（低密度奇偶校验）码，turbo码，turbo格状编码调制（TTCM） 或提供FEC能力的一些其他代码。

公开(公告)号：US08065588B2

公开(公告)日：2011-11-22

申请号：US11810991

申请日：2007-06-07

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： G11C29/00

CPC分类号： H03M13/2957 ,  H03M13/2757 ,  H03M13/2785 ,  H03M13/3972 ,  H03M13/6566 ,  H04L1/0071

摘要： Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (π) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors. This memory mapping allows collision-free reading and writing of updated information (as updated using parallel implemented turbo decoder) into memory banks.

摘要翻译： 具有二次多项式置换（QPP）交错的并行涡轮解码的公式灵活无冲突存储器存取。 提出了一种可以使用任何期望数量的并行实施的turbo解码处理器来执行已经使用QPP交织进行的turbo解码的装置。 呈现该方法以允许任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）在仍然使用QPP交织的所选实施例的情况下执行turbo编码信号的解码。 此外，无碰撞存储器映射MOD，C，W）提供了更多的自由度，用于选择满足具有任何期望数量的并行实现的turbo解码的并行turbo解码实现的特定二次多项式置换（QPP）交织（＆pgr） 处理器。 该存储器映射允许将更新的信息（使用并行实现的turbo解码器更新）的无冲突读写写入存储体。

公开(公告)号：US07975203B2

公开(公告)日：2011-07-05

申请号：US11810890

申请日：2007-06-07

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/2757 ,  H03M13/2775 ,  H03M13/3972 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6508 ,  H03M13/6525 ,  H03M13/6566

摘要： Quadratic polynomial permutation (QPP) interleaver providing hardware saving and flexible granularity adaptable to any possible turbo code block size. A means is presented by which only a very small number of coefficients need be stored to effectuate a wide variety of QPP interleaves as can be employed in the context of turbo coding. In one instance, to accommodate the approximate 6000 different turbo code block sizes in 3GPP LTE channel coding, only 5 different coefficient values need to be stored to effectuate a very broad range of QPP interleaves to be applied each of those various turbo code block sizes. Moreover, a few small number of dummy bits, if any, need to be employed to accommodate a very broad range of turbo code block sizes. It is noted that the QPP interleaving as described herein can be applied to turbo encoding and turbo decoding (e.g., including both interleaving and de-interleaving).

摘要翻译： 二次多项式置换（QPP）交织器，提供适用于任何可能的turbo码块大小的硬件保存和灵活的粒度。 提出了一种手段，其中仅需要非常少量的系数来存储多个QPP交织以便在turbo编码的上下文中使用。 在一种情况下，为了适应3GPP LTE信道编码中的大约6000个不同的Turbo码块大小，仅需要存储5个不同的系数值，以实现要应用那些各种turbo码块大小中的每一个的非常宽范围的QPP交织。 此外，需要采用少量的虚拟位（如果有的话）以适应非常宽范围的turbo码块大小。 注意，如本文所述的QPP交织可以应用于turbo编码和turbo解码（例如，包括交织和解交织两者）。

公开(公告)号：US07827473B2

公开(公告)日：2010-11-02

申请号：US11811014

申请日：2007-06-07

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/03

CPC分类号： G06F11/1008 ,  H03M13/2753 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3972

摘要： Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

摘要翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器。 本文提出了一种新颖的方法，通过该方法，使用任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）来执行turbo编码信号的解码，同时仍然使用所选择的ARP实施例（几乎 正则排列）交错。 选择所需数量的解码处理器，并且进行信息块（从而生成虚拟信息块）的非常轻微的修改以在除了一些虚拟解码周期之外的所有解码周期期间在所有解码处理器之间容纳该虚拟信息块。 此外，在解码处理器（例如，多个turbo解码器）和存储体（例如，多个存储器）之间提供无竞争的存储器映射。

公开(公告)号：US07661055B2

公开(公告)日：2010-02-09

申请号：US11323901

申请日：2005-12-30

申请人： Tak K. Lee ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Kelly Brian Cameron

发明人： Tak K. Lee ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Kelly Brian Cameron

IPC分类号： H03M13/00

CPC分类号： H04L1/0052 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/255 ,  H03M13/27 ,  H04L1/0057

摘要： Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.

摘要翻译： LDPC（低密度奇偶校验）解码器的部分并行实现。 提出了一种新颖的方法，通过该方法在对LDPC编码信号执行纠错解码时，在每个位节点处理和校验节点处理期间执行所选择的周期数。 每个位节点处理和校验节点处理的周期数不必相同。 可以在比特节点处理和校验节点处理两者期间使用至少一个功能块，组件，硬件部分或计算，从而通过有效利用处理资源来节省空间。 至少可以执行在每个位节点处理和校验节点处理期间执行2个周期的半并行方法。 或者，可以对比特节点处理和校验节点处理中的每一个执行多于2个周期。

公开(公告)号：US07644339B2

公开(公告)日：2010-01-05

申请号：US11709078

申请日：2007-02-21

申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/1162 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/616 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583

摘要： Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

摘要翻译： 提出了新的解码方法，通过该方法，立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息，而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息，而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比，使用这种方法，在给定时间段内可以执行两倍的解码迭代，然后更新整个LDPC矩阵的所有位边消息，以及 所以。 当结合最小和处理执行这种重叠方法时，也可以节省大量的内存。

公开(公告)号：US07617441B2

公开(公告)日：2009-11-10

申请号：US11472226

申请日：2006-06-21

申请人： Tak K. Lee ,  Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

发明人： Tak K. Lee ,  Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

IPC分类号： G06F11/00

CPC分类号： H03M13/11

摘要： Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).

摘要翻译： 具有具有CSI（循环移位身份）子矩阵的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码的高效构造。 这些构造的LDPC码可以在多输入多输出（MIMO）通信系统中实现。 一种LDPC码构造方法使用CSI子矩阵移位值，其移位值被检查，而不是奇偶校验矩阵（或其对应的子矩阵）内的非零元素位置。 当设计LDPC码时，该方法在LDPC码的相应二分图中找到并避免周期（或循环）是有效的。 另一种方法涉及基于GRS（Generalized Reed-Solomon）代码的LDPC码构造。 这些LDPC码可以在各种各样的通信设备中实现，包括在符合由IEEE 802.11n任务组（即正在努力开发的任务组）的建议实践和标准的无线通信系统中实现的通信设备 802.11 TGn（高吞吐量）标准）。

公开(公告)号：US20090199062A1

公开(公告)日：2009-08-06

申请号：US12362543

申请日：2009-01-30

申请人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

IPC分类号： H04L1/18 ,  H03M13/23 ,  G06F11/14 ,  G06F11/08

CPC分类号： H03M13/2957 ,  H03M13/2739 ,  H03M13/6306 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/653 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1819

摘要： Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.

摘要翻译： 用于速率匹配的虚拟限制缓冲区修改。 在通信设备内采用缩小尺寸的存储器模块以帮助存储根据turbo解码所采用的对数似然比（LLR）。 该架构也适用于除turbo码之外的其他类型的纠错码（ECC）。 选择存储器大小以匹配包含在传输内的编码比特数（例如，包括信息比特和冗余/奇偶校验比特）。 所接收的信号可以是根据混合自动重传请求（HARQ）传输而进行的各种传输。 当从第一HARQ传输计算的LLR不足以解码时，那些LLR被选择性地存储在存储器模块中。 当接收到对应于第二HARQ传输的LLR时，对应于第一HARQ传输和第二HARQ传输两者的LLR从存储器模块传递以用于解码。

公开(公告)号：US20090187804A1

公开(公告)日：2009-07-23

申请号：US12413552

申请日：2009-03-28

申请人： Ba-Zhong Shen ,  Christopher J. Hansen ,  Joseph Paul Lauer ,  Kelly Brian Cameron ,  Tak K. Lee ,  Hau Thien Tran

发明人： Ba-Zhong Shen ,  Christopher J. Hansen ,  Joseph Paul Lauer ,  Kelly Brian Cameron ,  Tak K. Lee ,  Hau Thien Tran

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H04L27/2626 ,  H03M13/1148 ,  H03M13/116 ,  H03M13/255 ,  H03M13/6362 ,  H04B7/0617 ,  H04L1/0057 ,  H04L1/0071 ,  H04L5/0023 ,  H04L27/2647 ,  H04L27/34

摘要： LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for communications using ECC. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).

摘要翻译： 在多输入多输出（MIMO）通信系统中实现的LDPC（低密度奇偶校验）编码和交织。 如本文所述，可以使用GRS或RS代码来生成各种不规则的LDPC码。 还提出了各种通信设备类型，其可以使用基于GRS的不规则LDPC码的纠错编码（ECC）以及适当选择的交织，以提供使用ECC的通信。 这些通信设备可以被实现在无线通信系统中，包括符合由IEEE 802.11n任务组（即，正在努力制定802.11Gn（高吞吐量）的标准的任务组）开发的推荐做法和标准的通信系统， ）。