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71.发明申请公开(公告)号：US20090094439A1
公开(公告)日：2009-04-09
申请号：US11919757
申请日：2005-05-11
CPC分类号： G06F9/30123 , G06F9/3012 , G06F9/3851
摘要： A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group. This has been found to provide a particularly efficient use of the registers within the data processing apparatus.
摘要翻译： 公开了一种采用多个寄存器组的数据处理装置和方法。 数据处理装置具有用于执行数据处理操作的处理逻辑和用于存储与处理逻辑相关联的数据的寄存器组。 寄存器组具有至少一个寄存器组，每个寄存器组具有多个寄存器组。 处理逻辑具有与定义如何使用该寄存器组的每个寄存器组相关联的操作状态，第一操作状态是其中在寄存器组中设置的每个寄存器用于支持处理逻辑的独立执行线程的状态，以及 第二操作状态是将寄存器组的寄存器组集中用于支持处理逻辑的单个执行线程的状态。 提供控制逻辑以根据与该寄存器组相关联的操作状态来控制如何使用每个寄存器组的寄存器组。 已经发现这提供了数据处理装置内寄存器的特别有效的用途。
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公开(公告)号：US20090044086A1
公开(公告)日：2009-02-12
申请号：US12222085
申请日：2008-08-01
申请人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
发明人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
IPC分类号： G06F11/30
CPC分类号： G06F11/1064
摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.
摘要翻译： 提供了一种数据处理装置，包括用于执行数据处理操作的处理电路，用于在执行数据处理操作时存储由处理电路进行访问的数据值的组合关联存储装置，用于对存储装置的每次访问执行的错误检测电路， 对所访问的数据值的错误检测操作，以及与存储设备相关联的用于执行一个或多个维护操作的维护电路。 处理电路被布置为向维护电路发出指示存储设备内的至少一个特定物理位置的错误检测维护请求，并且维护电路响应于错误检测维护请求，以对至少一个虚拟访问 在所述存储设备内的至少一个特定的物理位置，并且为所述处理电路提供由所述错误检测电路针对所述至少一个虚拟访问执行的错误检测操作导出的错误状态信息。
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73.发明授权公开(公告)号：US07447883B2
公开(公告)日：2008-11-04
申请号：US11501920
申请日：2006-08-10
IPC分类号： G06F9/32
CPC分类号： G06F12/0875 , G06F9/30058 , G06F9/30181 , G06F9/3806 , G06F12/0862 , G06F2212/6028 , Y02D10/13
摘要： A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.
摘要翻译： 数据处理系统包括指令提取电路2，指令队列4和其他处理电路6。 分支目标高速缓存（分支目标地址高速缓存8，分支目标指令高速缓存10或两者）分别用于存储从分支目标开始的分支目标地址或指令块。 当遇到分支指令时，控制电路12响应于指令队列4的内容，以确定分支目标高速缓存8,10中的存储资源是否应被分配给该分支指令。 当指令队列内的程序指令数量低于阈值数量和/或程序指令的估计执行时间低于阈值时间时，将分配分支目标缓存器8,10内的存储资源。
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公开(公告)号：US20080250217A1
公开(公告)日：2008-10-09
申请号：US12068449
申请日：2008-02-06
CPC分类号： G06F12/1483 , G06F9/30076
摘要： Access to memory address space is controlled by memory access control circuitry using access control data. The ability to change the access control data is controlled by domain control circuitry. Whether or not an instruction stored within a particular domain, being a set of memory addresses, is able to modify the access control data is dependent upon the domain concerned. Thus, the ability to change access control data can be restricted to instructions stored within particular defined locations within the memory address space thereby enhancing security. This capability allows systems to be provided in which call forwarding to an operating system can be enforced via call forwarding code and where trusted regions of the memory address space can be established into which a secure operating system may write data with increased confidence that that data will only be accessible by trusted software executing under control of a non-secure operating system.
摘要翻译： 使用访问控制数据的存储器访问控制电路控制对存储器地址空间的访问。 更改访问控制数据的能力由域控制电路控制。 作为一组存储器地址的存储在特定域内的指令是否能够修改访问控制数据取决于所涉及的域。 因此，改变访问控制数据的能力可以被限制为存储在存储器地址空间内的特定定义位置内的指令，从而增强安全性。 该功能允许提供系统，其中可以通过呼叫转移代码来实施对操作系统的呼叫转移，并且可以建立存储器地址空间的可信区域，安全操作系统可以以更高的置信度写入数据，该数据将 只能通过在非安全操作系统的控制下执行的可信软件来访问。
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公开(公告)号：US20080209133A1
公开(公告)日：2008-08-28
申请号：US11709279
申请日：2007-02-22
申请人： Emre Ozer , Stuart David Biles , Simon Andrew Ford
发明人： Emre Ozer , Stuart David Biles , Simon Andrew Ford
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0822 , Y02D10/13
摘要： A data processing apparatus and method are provided for managing cache coherency. The data processing apparatus comprises a plurality of processing units, each having a cache associated therewith, and each cache having indication circuitry containing segment filtering data. The indication circuitry is responsive to an address portion of an address specified by an access request from an associated processing unit to reference the segment filtering data in order to provide, for each of at least a subset of the segments of the associated cache, an indication as to whether the data is either definitely not stored in that segment or is potentially stored in that segment. Further, in accordance with the present invention, cache coherency circuitry is provided which employs a cache coherency protocol to ensure data accessed by each processing unit is up-to-date. The cache coherency circuitry has snoop indication circuitry associated therewith whose content is derived from the segment filtering data of each indication circuitry. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry is referenced to determine whether any of the caches require subjecting to a snoop operation. For each cache for which it is determined a snoop operation should be performed, the cache coherency circuitry is arranged to issue a notification to that cache identifying the snoop operation to be performed. By taking advantage of information already provided in association with each cache in order to form the content of the snoop indication circuitry, significant hardware cost savings are achieved when compared with prior art techniques. Further, through use of such an approach, it is possible in embodiments of the present invention to identify the snoop operation not only on a cache-by-cache basis, but also for a particular cache to identify which segments of that cache should be subjected to the snoop operation.
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