公开(公告)号：US5731239A

公开(公告)日：1998-03-24

申请号：US787193

申请日：1997-01-22

申请人： Harianto Wong ,  Kin Leong Pey ,  Lap Chan

发明人： Harianto Wong ,  Kin Leong Pey ,  Lap Chan

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66545

摘要： A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes. A second embodiment uses the self-aligned mask to form selectively a cobalt silicide on the polysilicon gate electrodes for low sheet resistance, while preventing the cobalt silicide from reacting with the adjacent titanium silicide source/drain regions.

摘要翻译： 已经实现了在场效应晶体管上制造低薄层电阻亚四分之一微米栅电极长度的方法。 该方法包括从表面上具有氮化硅层的导电掺杂多晶硅层在硅衬底上图案化栅电极。 在形成FET轻掺杂漏极（LDD），侧壁间隔物和具有钛触点的重掺杂源极/漏极接触区域之后，绝缘层被化学/机械地抛光回到栅极电极层上的氮化硅或氮氧化硅，至 形成平面自对准掩模。 进行预非晶化注入，并且在栅电极上选择性地形成硅化钛，导致小的晶粒尺寸和大大降低的薄层电阻。 自对准掩模防止离子注入损坏与FET栅电极相邻的浅源/漏区。 第二实施例使用自对准掩模在多晶硅栅电极上选择性地形成钴硅化物，用于低电阻，同时防止钴硅化物与相邻的硅化钛源极/漏极区发生反应。

公开(公告)号：US5652152A

公开(公告)日：1997-07-29

申请号：US636086

申请日：1996-04-22

申请人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

发明人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L21/74 ,  H01L21/441

CPC分类号： H01L21/743

摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.

摘要翻译： 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。

公开(公告)号：US09015629B2

公开(公告)日：2015-04-21

申请号：US13661687

申请日：2012-10-26

申请人： Lap Chan

发明人： Lap Chan

IPC分类号： G06F3/048 ,  G06F3/0481 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/0488 ,  H04M1/725

CPC分类号： G06F3/04817 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/04886 ,  H04M1/72519

摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, a second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.

摘要翻译： 描述了管理内容的示例系统和方法。 在一个实现中，一种方法访问第一组数据，第二组数据和菜单数据。 菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。 该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。 该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

公开(公告)号：US20140188552A1

公开(公告)日：2014-07-03

申请号：US13732790

申请日：2013-01-02

申请人： Lap Chan ,  Bin Duan

发明人： Lap Chan ,  Bin Duan

IPC分类号： G06Q30/02

CPC分类号： G06Q30/0269 ,  G06Q50/01

摘要： The disclosure generally describes computer-implemented methods, software, and systems for assessing a customer's mood by analyzing social network data. One computer-implemented method includes identifying a customer to monitor for mood, identifying at least one set of social network account information for the identified customer, accessing content items from at least one social network associated with the at least one set of social networking account information for the customer, determining a mood score for the identified customer based on the content items, and recording the determined mood score in a database.

摘要翻译： 本公开通常描述了通过分析社交网络数据来评估客户心情的计算机实现的方法，软件和系统。 一种计算机实现的方法包括识别客户以监视情绪，识别用于所识别的客户的至少一组社交网络帐户信息，从与至少一组社交网络帐户信息相关联的至少一个社交网络访问内容项目 对于客户，基于内容项目确定所识别的客户的心情得分，并将确定的心情得分记录在数据库中。

公开(公告)号：US08237531B2

公开(公告)日：2012-08-07

申请号：US11967270

申请日：2007-12-31

申请人： Ping Qiu ,  Chirn Chye Boon ,  Johnny Kok Wai Chew ,  Kiat Seng Yeo ,  Manh Anh Do ,  Lap Chan ,  Suh Fei Lim

发明人： Ping Qiu ,  Chirn Chye Boon ,  Johnny Kok Wai Chew ,  Kiat Seng Yeo ,  Manh Anh Do ,  Lap Chan ,  Suh Fei Lim

IPC分类号： H01F5/00 ,  H01F27/28 ,  H03J3/00

CPC分类号： H03J3/20 ,  H01F17/0006 ,  H01F2017/0073 ,  H03H11/48

摘要： An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.

摘要翻译： 具有高质量（Q）因子的电感器电路包括初级电感器和补偿子电路。 补偿子电路与主电感器电隔离。 补偿子电路与初级电感器磁耦合，以补偿初级电感器的损耗。

公开(公告)号：US08053340B2

公开(公告)日：2011-11-08

申请号：US11862213

申请日：2007-09-27

申请人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

发明人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

IPC分类号： H01L21/425 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

摘要： A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

摘要翻译： 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US07935632B2

公开(公告)日：2011-05-03

申请号：US11935415

申请日：2007-11-06

申请人： Wei Hua Tong ,  Lap Chan ,  K. Suresh Kumar ,  Miow Chin Tan

发明人： Wei Hua Tong ,  Lap Chan ,  K. Suresh Kumar ,  Miow Chin Tan

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/78

摘要： Formation of metal pipes resulting from formation of metal silicide contacts are reduced or avoided. To reduce formation of metal pipes, an epitaxial layer is formed over the diffusion region on which the metal silicide contact is formed. The epitaxial layer reduces defects which enhances diffusion of metal atoms or molecules.

摘要翻译： 减少或避免由形成金属硅化物接触导致的金属管的形成。 为了减少金属管的形成，在其上形成有金属硅化物接触的扩散区域上形成外延层。 外延层减少了增强金属原子或分子扩散的缺陷。

公开(公告)号：US07570144B2

公开(公告)日：2009-08-04

申请号：US11750341

申请日：2007-05-18

申请人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

发明人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F17/0013 ,  H01F19/08 ,  H01F27/2804 ,  H01F41/041 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/4902 ,  H01L2924/00

摘要： An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.

摘要翻译： 集成变压器结构包括与横向轴线相关联的第一线圈元件，第一线圈元件具有至少一匝。 第一线圈元件包括设置在第一横向水平面上的第一部分和设置在第二横向水平面上的第二部分。 第一和第二横向水平面沿着所述横向轴线相互间隔开。 第一和第二部分从所述轴线横向移位不同的相应距离。 所述第一线圈元件的至少一个交叉部分，其中所述第一线圈元件被配置为提供通过所述交叉部分穿过所述交叉部分的所述第一线圈元件的所述第一部分的至少一部分的导电路径，并且随后通过 第一线圈元件的第二部分的至少一部分，其中沿着所述路径的流动方向的任何变化在横向方向上小于90°。

公开(公告)号：US20060206852A1

公开(公告)日：2006-09-14

申请号：US11078820

申请日：2005-03-10

申请人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

发明人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.

摘要翻译： 提供具有不连续点的试验半导体光掩模设计，将每个不连续点视为模拟光源。 聚焦每个模拟光源的模拟光，并计算聚焦模拟光的合成图像强度，以验证试验半导体光掩模设计。 试制半导体光掩模设计锐化。 生成光掩模设计规范用于制造这种光掩模。

公开(公告)号：US20060194397A1

公开(公告)日：2006-08-31

申请号：US11391506

申请日：2006-03-28

申请人： Lay Choo ,  James Lee ,  Lap Chan

发明人： Lay Choo ,  James Lee ,  Lap Chan

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/949

摘要： In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.