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    System and method for designing semiconductor photomasks
    1.
    发明授权
    System and method for designing semiconductor photomasks 有权
    设计半导体光掩模的系统和方法

    公开(公告)号：US07313780B2

    公开(公告)日：2007-12-25

    申请号：US11078820

    申请日：2005-03-10

    申请人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

    发明人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.

    摘要翻译： 提供具有不连续点的试验半导体光掩模设计，将每个不连续点视为模拟光源。 聚焦每个模拟光源的模拟光，并计算聚焦模拟光的合成图像强度，以验证试验半导体光掩模设计。 试制半导体光掩模设计锐化。 生成光掩模设计规范用于制造这种光掩模。

    Structure and method to form source and drain regions over doped depletion regions
    2.
    发明申请
    Structure and method to form source and drain regions over doped depletion regions 有权
    在掺杂耗尽区上形成源极和漏极区的结构和方法

    公开(公告)号：US20070178652A1

    公开(公告)日：2007-08-02

    申请号：US11706891

    申请日：2007-02-14

    申请人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Woh Leong ,  Kheng Tee

    发明人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Woh Leong ,  Kheng Tee

    IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/425

    CPC分类号： H01L29/0847 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/961

    摘要： A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

    摘要翻译： 减小晶体管中源/漏区的结电容的结构和方法。 栅极结构形成在第一导电类型的衬底上。 我们通过使用栅极结构作为掩模将作为第二导电类型的离子注入到衬底来进行掺杂耗尽区域注入，以在源极/漏极区域之下形成掺杂的耗尽区域并从源极/漏极区域分离。 掺杂的耗尽区具有杂质浓度和厚度，使得掺杂的耗尽区由于在掺杂耗尽区和衬底之间可建立的内置势而耗尽。 掺杂耗尽区和衬底在源/漏区和掺杂耗尽区之间形成耗尽区。 我们通过将具有第二导电类型的离子注入到衬底中来形成S / D区域来进行S / D植入。 掺杂的耗尽区域和耗尽区域减小了源/漏区域和衬底之间的电容。

    Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing
    4.
    发明授权
    Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing 有权
    使用激光退火形成应变Si沟道和Si1-xGex源极/漏极结构

    公开(公告)号：US07892905B2

    公开(公告)日：2011-02-22

    申请号：US11195196

    申请日：2005-08-02

    申请人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

    发明人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

    IPC分类号： H01L31/0216 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

    摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

    摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的预非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。

    System and method for designing semiconductor photomasks
    5.
    发明申请
    System and method for designing semiconductor photomasks 有权
    设计半导体光掩模的系统和方法

    公开(公告)号：US20060206852A1

    公开(公告)日：2006-09-14

    申请号：US11078820

    申请日：2005-03-10

    申请人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

    发明人： Andrew Khoh ,  Byong-Il Choi ,  Lap Chan ,  Ganesh Samudra ,  Yihong Wu

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.

    摘要翻译： 提供具有不连续点的试验半导体光掩模设计，将每个不连续点视为模拟光源。 聚焦每个模拟光源的模拟光，并计算聚焦模拟光的合成图像强度，以验证试验半导体光掩模设计。 试制半导体光掩模设计锐化。 生成光掩模设计规范用于制造这种光掩模。

    Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing
    7.
    发明申请
    Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing 有权
    使用激光退火形成应变Si沟道和Si1-xGex源极/漏极结构

    公开(公告)号：US20070032026A1

    公开(公告)日：2007-02-08

    申请号：US11195196

    申请日：2005-08-02

    申请人： Kuang Ong ,  Kin Pey ,  King Chui ,  Ganesh Samudra ,  Yee Yeo ,  Yung Chong

    发明人： Kuang Ong ,  Kin Pey ,  King Chui ,  Ganesh Samudra ,  Yee Yeo ,  Yung Chong

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

    摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

    摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的前非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。

    Structure and method to form source and drain regions over doped depletion regions
    8.
    发明申请
    Structure and method to form source and drain regions over doped depletion regions 有权
    在掺杂耗尽区上形成源极和漏极区的结构和方法

    公开(公告)号：US20050156253A1

    公开(公告)日：2005-07-21

    申请号：US10761613

    申请日：2004-01-21

    申请人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Leong ,  Kheng Tee

    发明人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Leong ,  Kheng Tee

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/961

    摘要： A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

    摘要翻译： 减小晶体管中源/漏区的结电容的结构和方法。 栅极结构形成在第一导电类型的衬底上。 我们通过使用栅极结构作为掩模将作为第二导电类型的离子注入到衬底来进行掺杂耗尽区域注入，以在源极/漏极区域之下形成掺杂的耗尽区域并从源极/漏极区域分离。 掺杂耗尽区具有杂质浓度和厚度，使得掺杂的耗尽区由于在掺杂的耗尽区和衬底之间可建立的内置势而耗尽。 掺杂耗尽区和衬底在源/漏区和掺杂耗尽区之间形成耗尽区。 我们通过将具有第二导电类型的离子注入到衬底中来形成S / D区域来进行S / D植入。 掺杂的耗尽区域和耗尽区域减小了源/漏区域和衬底之间的电容。