公开(公告)号：US20230014304A1

公开(公告)日：2023-01-19

申请号：US17955188

申请日：2022-09-28

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

公开(公告)号：US20230004289A1

公开(公告)日：2023-01-05

申请号：US17942388

申请日：2022-09-12

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.

公开(公告)号：US20220405199A1

公开(公告)日：2022-12-22

申请号：US17653323

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F12/02 ,  G06F12/0891

Abstract: According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.

公开(公告)号：US20220350530A1

公开(公告)日：2022-11-03

申请号：US17684551

申请日：2022-03-02

Applicant: Kioxia Corporation

Inventor： Hideki YOSHIDA ,  Shinichi KANNO ,  Naoki ESAKA

IPC: G06F3/06

Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

公开(公告)号：US20220350489A1

公开(公告)日：2022-11-03

申请号：US17869569

申请日：2022-07-20

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G11C29/52 ,  G06F12/02

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

公开(公告)号：US20220300214A1

公开(公告)日：2022-09-22

申请号：US17836397

申请日：2022-06-09

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.

公开(公告)号：US20220300172A1

公开(公告)日：2022-09-22

申请号：US17412028

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Shinichi KANNO ,  Yuki SASAKI

IPC: G06F3/06

Abstract: A memory system may be connected to a host device. The memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory to reduce an amount of power consumption of the memory system based on a first instruction received from a host device connected to the memory system.

公开(公告)号：US20220223552A1

公开(公告)日：2022-07-14

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: H01L23/00 ,  H01L23/544 ,  G06F11/07

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20220214966A1

公开(公告)日：2022-07-07

申请号：US17699660

申请日：2022-03-21

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Naoki ESAKA

IPC: G06F12/02 ,  G06F12/0871 ,  G06F13/40 ,  G06F13/16 ,  G06F12/0868

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

公开(公告)号：US20220147283A1

公开(公告)日：2022-05-12

申请号：US17586174

申请日：2022-01-27

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Koichi NAGAI

IPC: G06F3/06

Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.