公开(公告)号：US20220223552A1

公开(公告)日：2022-07-14

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: H01L23/00 ,  H01L23/544 ,  G06F11/07

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20220085046A1

公开(公告)日：2022-03-17

申请号：US17400627

申请日：2021-08-12

Applicant: Kioxia Corporation

Inventor： Takashi FUKUSHIMA ,  Toshiyuki SASAKI

IPC: H01L27/11568 ,  H01L27/11521

Abstract: A semiconductor memory device includes a substrate; a plurality of first conductive layers and first insulating layers stacked in alternation; a first semiconductor layer opposed to first conductive layers and first insulating layers; a second semiconductor layer; a second insulating layer that covers outer peripheral surface of the first semiconductor layer; and a third insulating layer disposed at a position different from first conductive layers, first insulating layers, and the second insulating layer, the third insulating layer having one end in contact with the second semiconductor, the third insulating layer having another end farther from the second semiconductor layer than the second insulating layer. A metal oxide film is disposed on a surface on the third insulating layer side of the second insulating layer. A metal oxide film is absent on a surface on the third insulating layer side of the plurality of first insulating layers.

公开(公告)号：US20230301088A1

公开(公告)日：2023-09-21

申请号：US17806111

申请日：2022-06-09

Applicant: Kioxia Corporation

Inventor： Saho OHSAWA ,  Kenichi FUJII ,  Takashi FUKUSHIMA ,  Hiroyuki OHTORI ,  Kaihei KATOU ,  Masaki KATO ,  Ryosuke SAWABE ,  Yuji SAKAI

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L29/4234 ,  H01L29/513

Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a gate electrode layer containing at least one element selected from a group consisting of molybdenum (Mo), tungsten (W), ruthenium (Ru), and cobalt (Co); a first insulating layer provided between the semiconductor layer and the gate electrode layer; a charge storage layer provided between the first insulating layer and the gate electrode layer; a second insulating layer provided between the charge storage layer and the gate electrode layer; a third insulating layer provided between the second insulating layer and the gate electrode layer; and a metal oxide layer provided between the third insulating layer and the gate electrode layer and containing at least one first metal element selected from a group consisting of titanium (Ti), molybdenum (Mo), tungsten (W), and tantalum (Ta).

公开(公告)号：US20230262973A1

公开(公告)日：2023-08-17

申请号：US18305685

申请日：2023-04-24

Applicant: Kioxia Corporation

Inventor： Kaihei KATO ,  Takashi FUKUSHIMA ,  Kazutaka SUZUKI

IPC: H10B41/27 ,  G11C5/06 ,  G11C5/02 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B41/27 ,  G11C5/06 ,  G11C5/025 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor storage device includes a substrate having a surface, a first conductive layer 25 disposed on a substrate and extending in an X direction parallel to the surface of the substrate; a second conductive layer 25 that disposed on the first conductive layer 25 and extending in the X direction; an insulation plug 30 disposed on the substrate, extends in a Z direction intersecting with the X direction, and intersects with the first conductive layer 25; and a contact plug CC disposed on the first insulation plug 30, extends in the Z direction, and intersects with the second conductive layer 25.

公开(公告)号：US20230276627A1

公开(公告)日：2023-08-31

申请号：US17901606

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Takashi FUKUSHIMA ,  Kaihei KATOU ,  Kenichiro TORATANI ,  Ryota FUJITSUKA ,  Junya FUJITA ,  Atsushi FUKUMOTO ,  Motoki FUJII ,  Yuki WAKISAKA ,  Kazuya HATANO

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: A semiconductor device according to the present embodiment comprises a stack including a plurality of electrode films stacked in a first direction to be separated from each other. A column portion extends in the stack in the first direction and includes a semiconductor layer, and has memory cells at respective intersections of the semiconductor layer and the electrode films. A dividing portion extends in the stack in the first direction and a second direction crossing the first direction, divides the electrode films in a third direction crossing the first direction and the second direction, and includes an insulator. A first film is provided between the insulator and an end surface in the third direction of each of the electrode films and contains a first metal and silicon.

公开(公告)号：US20230073505A1

公开(公告)日：2023-03-09

申请号：US17683963

申请日：2022-03-01

Applicant: Kioxia Corporation

Inventor： Takashi FUKUSHIMA ,  Yuji SAKAI ,  Hiroshi ITOKAWA ,  Tatsunori ISOGAI ,  Ryosuke SAWABE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor storage device includes: a plurality of conductive layers arranged in a first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage layer provided between the plurality of conductive layers and the semiconductor layer; a first structure disposed apart from the semiconductor layer in a second direction intersecting the first direction, extending in a third direction intersecting the first direction and the second direction, and facing the plurality of conductive layers; and a plurality of first nitride films containing nitrogen (N), and covering surfaces of the plurality of conductive layers facing the first structure.

公开(公告)号：US20220204270A1

公开(公告)日：2022-06-30

申请号：US17694532

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: B65G1/137

Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

公开(公告)号：US20210407905A1

公开(公告)日：2021-12-30

申请号：US17447332

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Takashi SHIMIZU ,  Takashi FUKUSHIMA ,  Naomi FUKUMAKI ,  Hiroko TAHARA ,  Kenichi IDE

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers that each include tungsten; a plurality of insulating films that include a stacked portion and a first projecting portion projecting; a semiconductor layer extending through an inside of a stacked body; a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer; a plurality of second conductive layers that are each arranged on the first projecting portion in such a manner as to be in contact with a single first conductive layer and that include silicon containing an impurity; and a plurality of contact plugs that are each provided on a single second conductive layer in such a manner as to be in contact with the single second conductive layer.

公开(公告)号：US20210159239A1

公开(公告)日：2021-05-27

申请号：US17007675

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Kaihei KATO ,  Takashi FUKUSHIMA ,  Kazutaka SUZUKI

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: A semiconductor storage device includes a substrate having a surface, a first conductive layer 25 disposed on a substrate and extending in an X direction parallel to the surface of the substrate; a second conductive layer 25 that disposed on the first conductive layer 25 and extending in the X direction; an insulation plug 30 disposed on the substrate, extends in a Z direction intersecting with the X direction, and intersects with the first conductive layer 25; and a contact plug CC disposed on the first insulation plug 30, extends in the Z direction, and intersects with the second conductive layer 25.

公开(公告)号：US20210149568A1

公开(公告)日：2021-05-20

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.