公开(公告)号：US11184085B1

公开(公告)日：2021-11-23

申请号：US17010857

申请日：2020-09-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Elad Mentovich ,  Liron Mula ,  Yuval Itkin

IPC: G02F1/00 ,  G02F2/00 ,  H04B10/00 ,  H04J14/00 ,  H04B10/03 ,  H04B10/25 ,  H04B10/27 ,  H04B10/50 ,  G02B6/42 ,  H04B10/40 ,  H04L9/32 ,  H04L9/08 ,  H04L9/06 ,  H04B10/66

Abstract: An electro-optical (EO) interconnect assembly includes an optical fiber, and first and second EO transceivers. The first and second EO transceivers, which are coupled to respective ends of the optical fiber, are configured to (i) connect to respective first and second network devices, (ii) exchange electrical signals with the first and second network devices, (iii) convert between the electrical signals and optical signals, and exchange the optical signals with one another over the optical fiber, and (iv) conduct with one another, over the optical fiber, a secure challenge-response transaction, and to initiate a responsive action upon failure of the challenge-response transaction.

公开(公告)号：US11070304B1

公开(公告)日：2021-07-20

申请号：US16799873

申请日：2020-02-25

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Liron Mula ,  Avraham Ganor ,  Avi Urman ,  Aviad Raveh ,  Yuval Itkin ,  Oren Matus

IPC: H04J3/06

Abstract: In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.

公开(公告)号：US20210141413A1

公开(公告)日：2021-05-13

申请号：US16779611

申请日：2020-02-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Liron Mula ,  Ariel Almog ,  Aviad Raveh ,  Yuval Itkin

IPC: G06F1/12 ,  H03C3/09

Abstract: In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.

公开(公告)号：US09344117B2

公开(公告)日：2016-05-17

申请号：US13839193

申请日：2013-03-15

Applicant: Mellanox Technologies Ltd.

Inventor： Liron Mula ,  Ran Ravid ,  Chen Gaist ,  Omer Sella ,  Oren Tzvi Sela

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/37

CPC classification number: H03M13/1515 ,  H03M13/153 ,  H03M13/1575 ,  H03M13/3715

Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.

Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。