公开(公告)号：US08464134B2

公开(公告)日：2013-06-11

申请号：US12436155

申请日：2009-05-06

申请人： Idan Alrod ,  Eran Sharon ,  Menahem Lasser

发明人： Idan Alrod ,  Eran Sharon ,  Menahem Lasser

IPC分类号： G06F11/00

CPC分类号： G06F11/1068

摘要： Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (ii) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.

摘要翻译： 本发明的实施例涉及对至少一个固态存储器块维持擦除计数的方法和装置。 根据存储器块的相关擦除次数，从固态存储器读取的数据中的错误被校正。 在一些实施例中，可以根据从其读取数据的存储器块的相关联的擦除计数来实现以下纠错操作中的一个或多个：（i）选择解码器和/或解码器模式; （ii）进行使用较轻权重解码器（模式）和/或较重权重解码器（模式）和/或更快解码器（模式）和/或较慢解码器（模式）来尝试校正错误的决定; （iii）确定模式转换和/或纠错尝试资源预算; （iv）确定多个软比特; 和（v）选择解码总线宽度大小。

公开(公告)号：US20130111113A1

公开(公告)日：2013-05-02

申请号：US13596926

申请日：2012-08-28

申请人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger ,  Menahem Lasser

发明人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger ,  Menahem Lasser

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/0483

摘要： A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.

摘要翻译： 公开了一种用于在主机设备和在闪存芯片上制造的闪存设备（例如，NAND闪存设备）之间进行接口的NAND控制器。 在一些实施例中，本公开的NAND控制器包括制造在控制器管芯上的电子电路，控制器管芯与闪存管芯不同，第一接口（例如，主机型接口，例如，NAND接口），用于在 电子电路和闪存设备，以及用于在控制器和主机设备之间进行接口的第二接口（例如，闪存型接口），其中第二接口是NAND接口。 根据一些实施例，第一接口是管芯间接口。 根据一些实施例，第一接口是NAND接口。 还公开了包括当前公开的NAND控制器的系统。 还公开了用于组装上述系统以及用于使用NAND控制器读取和写入数据的方法。

公开(公告)号：US08386868B2

公开(公告)日：2013-02-26

申请号：US12103784

申请日：2008-04-16

申请人： Menahem Lasser

发明人： Menahem Lasser

IPC分类号： G06F11/30

CPC分类号： G06F11/1068

摘要： Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, first data is written to the memory, and a value(s) of an operational parameter(s) that is a consequence of the writing of the first data is determined. Second data is read from the memory, and the value(s) of the operational parameter(s) may be used when correcting errors in the second data. In some embodiments, the first data is the same as the second data. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.

摘要翻译： 公开了一种用于处理存储器中的纠错的方法，装置和计算机可读介质。 在一些实施例中，将第一数据写入存储器，并且确定作为写入第一数据的结果的操作参数的值。 从存储器读取第二数据，并且可以在校正第二数据中的错误时使用操作参数的值。 在一些实施例中，第一数据与第二数据相同。 目前公开的教导可应用于包括（i）诸如闪存，磁存储器和光存储器的非易失性存储器和（ii）诸如SRAM或DRAM之类的易失性存储器的任何种类的存储器。

公开(公告)号：US08321757B2

公开(公告)日：2012-11-27

申请号：US12143796

申请日：2008-06-22

申请人： Avraham Meir ,  Menahem Lasser

发明人： Avraham Meir ,  Menahem Lasser

IPC分类号： G11C29/00

CPC分类号： G06F11/1068

摘要： Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, after an attempt is made to write original data to a ‘target’ memory, data is read back from the target memory in a ‘first read operation’, thereby generating first read data. After the first read operation, the first read data is compared to the original data and/or an indication of a difference between the original data and the first data is determined. The information obtained by effecting the data-comparison and/or information related to the difference indication is used when correcting errors in data read back from the target memory in a ‘second read operation.’. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.

摘要翻译： 公开了一种用于处理存储器中的纠错的方法，装置和计算机可读介质。 在一些实施例中，在尝试将原始数据写入目标存储器之后，在第一读取操作中从目标存储器读回数据，从而生成第一读取数据。 在第一读取操作之后，将第一读取数据与原始数据进行比较和/或确定原始数据与第一数据之间的差异的指示。 当在第二读取操作中校正从目标存储器读回的数据中的错误时，使用通过进行与差异指示相关的数据比较和/或信息而获得的信息。本公开的教导可应用于任何种类的存储器 包括（i）非易失性存储器，例如闪速存储器，磁存储器和光存储器，以及（ii）诸如SRAM或DRAM之类的易失性存储器。

公开(公告)号：US08291295B2

公开(公告)日：2012-10-16

申请号：US12539417

申请日：2009-08-11

申请人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger ,  Menahem Lasser

发明人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger ,  Menahem Lasser

IPC分类号： G11C29/00

CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/0483

摘要： A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.

摘要翻译： 公开了一种用于在主机设备和在闪存芯片上制造的闪存设备（例如，NAND闪存设备）之间进行接口的NAND控制器。 在一些实施例中，本公开的NAND控制器包括制造在控制器管芯上的电子电路，控制器管芯与闪存管芯不同，第一接口（例如，主机型接口，例如，NAND接口），用于在 电子电路和闪存设备，以及用于在控制器和主机设备之间进行接口的第二接口（例如，闪存型接口），其中第二接口是NAND接口。 根据一些实施例，第一接口是管芯间接口。 根据一些实施例，第一接口是NAND接口。 还公开了包括当前公开的NAND控制器的系统。 还公开了用于组装上述系统以及用于使用NAND控制器读取和写入数据的方法。

公开(公告)号：US08204169B2

公开(公告)日：2012-06-19

申请号：US12113293

申请日：2008-05-01

申请人： Dov Moran ,  Avi Klein ,  Itzhak Pomerantz ,  Menahem Lasser ,  Eyal Bychkov ,  Eran Leibinger ,  Avraham Meir

发明人： Dov Moran ,  Avi Klein ,  Itzhak Pomerantz ,  Menahem Lasser ,  Eyal Bychkov ,  Eran Leibinger ,  Avraham Meir

IPC分类号： G06M11/00

CPC分类号： B65B57/20 ,  G06C1/00 ,  G11C11/5621 ,  G11C2216/08

摘要： Methods and systems for counting items in storage containers in an array of at least two storage containers, the method including the steps of: providing a storage array of at least two storage containers, each of the storage containers containing an unknown amount of items; providing a receiving array of at least two receiving containers, wherein the receiving containers initially contain no items; extracting a layer of the items from the storage array; inserting the layer into corresponding locations in the receiving array; repeating the steps of extracting and inserting while at least one of the storage containers is not empty; counting, for each storage container in the storage array, a productive-extraction amount; and reporting, for at least some of the storage containers, the productive-extraction amount from each storage container. Preferably, the method further includes recovering a storage identity upon recovery from a system failure that erases the productive-extraction amount.

摘要翻译： 用于计数至少两个存储容器的阵列中的存储容器中的物品的方法和系统，所述方法包括以下步骤：提供至少两个存储容器的存储阵列，每个存储容器包含未知数量的物品; 提供至少两个接收容器的接收阵列，其中所述接收容器最初不包含物品; 从存储阵列提取物品层; 将层插入接收阵列中的相应位置; 重复提取和插入的步骤，同时至少一个存储容器不为空; 对存储阵列中的每个存储容器进行计数，生产提取量; 并且对于至少一些储存容器报告来自每个储存容器的生产提取量。 优选地，该方法还包括在从擦除生产提取量的系统故障恢复时恢复存储身份。

公开(公告)号：US08145830B2

公开(公告)日：2012-03-27

申请号：US12767094

申请日：2010-04-26

申请人： Menahem Lasser

发明人： Menahem Lasser

IPC分类号： G06F13/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0893 ,  G11C11/5628 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.

摘要翻译： 闪速存储器装置包括存储区域，其具有主存储器部分和高速缓存存储器部分，其存储比主存储器部分少的至少一个比特的比特; 以及控制器，其根据从主机接收到的至少一个高速缓存命令来管理所述高速缓冲存储器部分和所述主存储器部分之间的数据传输。 控制器对数据传输的管理包括将新数据从主机传输到高速缓冲存储器部分，将数据从高速缓冲存储器部分复制到主存储器部分，并控制（启用/禁用）高速缓存清理操作的调度。

公开(公告)号：US08108588B2

公开(公告)日：2012-01-31

申请号：US10445358

申请日：2003-05-27

申请人： Dana Gross ,  Menahem Lasser

发明人： Dana Gross ,  Menahem Lasser

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C2216/22

摘要： A memory device includes an executable flash memory partition and a non-executable partition, both partitions being fabricated on a common die. Preferably, both partitions are fabricated using the same flash memory technology. Most preferably, the flash cells of both partitions have insulating floating gates.

摘要翻译： 存储器设备包括可执行闪存分区和不可执行分区，两个分区被制造在公共模具上。 优选地，使用相同的闪速存储器技术来制造两个分区。 最优选地，两个分区的闪存单元具有绝缘浮动栅极。

公开(公告)号：US08086931B2

公开(公告)日：2011-12-27

申请号：US12648313

申请日：2009-12-29

申请人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod ,  Menahem Lasser

发明人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod ,  Menahem Lasser

IPC分类号： H03M13/00

CPC分类号： H03M13/2927 ,  G06F11/1068 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/1545 ,  H03M13/2903 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/6362

摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

摘要翻译： 要编码的数据位被分割成多个子组。 每个子组被分别编码以产生相应的码字。 所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。 最终码字是缩短的码字和浓缩比特的组合。 最终码字的表示被分割成选定的子集和多个剩余子集。 每个剩余子集被单独解码。 如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。 如果编码和解码是系统的，则所选择的子集是奇偶校验位。

公开(公告)号：US08069380B2

公开(公告)日：2011-11-29

申请号：US12755519

申请日：2010-04-07

申请人： Mark Murin ,  Menahem Lasser ,  Avraham Meir

发明人： Mark Murin ,  Menahem Lasser ,  Avraham Meir

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/48 ,  G01R31/318513 ,  G11C29/1201 ,  G11C2029/0401 ,  G11C2029/1208

摘要： A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

摘要翻译： 闪存设备包括驻留在至少一个闪存存储器模块上的闪存。 闪存设备还包括驻留在闪存控制器管芯上的与至少一个闪存管芯分离的闪存控制器。 闪存和闪存控制器驻留在，驻留在或连接到公共外壳。 闪存控制器被配置为执行至少一个测试程序来测试至少一个闪存芯片。