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    READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME
    71.
    发明公开
    READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME 审中-公开

    公开(公告)号：US20240177781A1

    公开(公告)日：2024-05-30

    申请号：US18388506

    申请日：2023-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Jun Wan ,  Zhenming Zhou

    IPC: G11C16/28 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/24

    Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.

    Memory read operation using a voltage pattern based on a read command type
    72.
    发明授权
    Memory read operation using a voltage pattern based on a read command type 有权

    公开(公告)号：US11972122B2

    公开(公告)日：2024-04-30

    申请号：US17817465

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

    CHARGE LOSS MITIGATION THROUGH DYNAMIC PROGRAMMING SEQUENCE
    73.
    发明公开
    CHARGE LOSS MITIGATION THROUGH DYNAMIC PROGRAMMING SEQUENCE 审中-公开

    公开(公告)号：US20240061588A1

    公开(公告)日：2024-02-22

    申请号：US17889873

    申请日：2022-08-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0644

    Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

    3D NAND MEMORY WITH BUILT-IN CAPACITOR
    76.
    发明公开
    3D NAND MEMORY WITH BUILT-IN CAPACITOR 审中-公开

    公开(公告)号：US20240046998A1

    公开(公告)日：2024-02-08

    申请号：US17879356

    申请日：2022-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G11C16/30

    CPC classification number: G11C16/30

    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

    ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS
    78.
    发明公开
    ERROR DETECTION FOR PROGRAMMING SINGLE LEVEL CELLS 审中-公开

    公开(公告)号：US20240028214A1

    公开(公告)日：2024-01-25

    申请号：US17871804

    申请日：2022-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Tomer Tzvi Eliash ,  Yu-Chung Lien

    IPC: G06F11/07 ,  G06F3/06

    CPC classification number: G06F11/0769 ,  G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673

    Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.

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