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公开(公告)号：US12248697B2
公开(公告)日：2025-03-11
申请号：US17830802
申请日：2022-06-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Li-Te Chang , Zhenming Zhou
IPC: G06F3/06
Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.
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公开(公告)号：US20250044953A1
公开(公告)日：2025-02-06
申请号：US18797445
申请日：2024-08-07
Applicant: Micron Technology, Inc.
Inventor： Tomer Tzvi Eliash , Yu-Chung Lien
IPC: G06F3/06 , G01R19/165 , G06F11/07 , G11C29/08 , G11C29/50
Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.
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公开(公告)号：US20250037774A1
公开(公告)日：2025-01-30
申请号：US18917774
申请日：2024-10-16
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Jun Wan , Zhenming Zhou
Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components includes a processing device that initiates a corrective read (CR) operation on a set of memory components. The set of memory components includes a pillar that includes a channel and a plurality of transistors. The processing device applies a charge to a first word line (WL) comprising a first transistor of a plurality of transistors to neutralize charges in the channel and senses a charge distribution of a second WL comprising a second transistor of the plurality of transistors adjacent to the first transistor based on the charge applied to the first WL that neutralized the charges in the channel.
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公开(公告)号：US20250029665A1
公开(公告)日：2025-01-23
申请号：US18906579
申请日：2024-10-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Zhenming Zhou
Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a two-pass programming command with respect to a set of memory cells. The processing device is further to determine a value of a metric reflecting a reliability of the set of memory cells. The processing device is further to determine, from a data structure, a delay duration and a subset of the set of memory cells based on the value of the metric. The data structure correlates metric values with respective delay duration values and with respective subsets of memory cells. The processing device is further to perform a two-pass programming operation with respect to the set of memory cells. The two-pass programming operation includes the delay duration between a first pass of the two-pass programming operation and a second pass of the two-pass programming operation.
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公开(公告)号：US20250029663A1
公开(公告)日：2025-01-23
申请号：US18745731
申请日：2024-06-17
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Zhenming Zhou
Abstract: Apparatuses and methods for performing corrective read operations on a partially programmed block are provided. One example apparatus can include a controller configured to perform a corrective read operation on a target word line of a partially programmed block, wherein the corrective read operation includes applying a first corrective read voltage signal to the target word line during the corrective read operation, applying a second corrective read voltage signal to a word line adjacent to the target word line during the corrective read operation, applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation, and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the target word line during the corrective read operation.
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Patent Agency Ranking
公开(公告)号：US20240370364A1
公开(公告)日：2024-11-07
申请号：US18633288
申请日：2024-04-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Zhongguang Xu , Peng Zhang , Zhenming Zhou
IPC: G06F12/02
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: identifying a block of the memory device, the block spanning over a plurality of decks; determining whether a set of memory cells of the memory device is disposed in a first deck of the block or a second deck of the block, the first deck having a memory reliability metric satisfying a first criterion pertaining to a reliability of a deck, and the second deck having a memory reliability metric not satisfying the first criterion; selecting, based on the determination, an erase policy for performing an erase operation with respect to the set of memory cells; and causing the erase operation to be performed with respect to the set of memory cells in accordance with the erase policy.
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公开(公告)号：US20240304256A1
公开(公告)日：2024-09-12
申请号：US18666063
申请日：2024-05-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Zhenming Zhou
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/32
Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells. The processing device is further to determine a value of a metric reflecting reliability of a subset of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a two-pass programming operation with respect to the subset of memory cells. The two-pass programming operation includes the delay.
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公开(公告)号：US12079079B2
公开(公告)日：2024-09-03
申请号：US17897183
申请日：2022-08-28
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Zhenming Zhou , Wei Wang
CPC classification number: G06F11/1068 , G06F11/1489 , G06F11/3409
Abstract: A method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. The method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
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公开(公告)号：US20240203502A1
公开(公告)日：2024-06-20
申请号：US18527658
申请日：2023-12-04
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Zhenming Zhou
CPC classification number: G11C16/10 , G11C16/26 , G11C16/3459
Abstract: A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A bitline voltage adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default bitline voltage is adjusted by the bitline voltage adjustment value to generate an adjusted bitline voltage. The program operation on the set of vertically stacked memory cells is performed using the adjusted bitline voltage.
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公开(公告)号：US20240194279A1
公开(公告)日：2024-06-13
申请号：US18524721
申请日：2023-11-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tomer Tzvi Eliash , Yu-Chung Lien
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/32
Abstract: A system can include a plurality of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices, to perform operations comprising: determining whether a parameter of a power supply of the volatile memory device satisfies a threshold criterion; responsive to determining that the parameter of the power supply satisfies the threshold criterion, modifying a value of a parameter of a program operation; and programming, using the modified value of the parameter, designated data stored on the volatile memory device to a designated location on the non-volatile memory device.
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