公开(公告)号：US07004029B2

公开(公告)日：2006-02-28

申请号：US10856858

申请日：2004-06-01

申请人： Minekazu Sakai

发明人： Minekazu Sakai

IPC分类号： G01P15/125 ,  G01P15/00

CPC分类号： G01P15/125

摘要： In a semiconductor acceleration sensor (S1), above one side of a first silicon substrate (10) made of a semiconductor and serving as a fixed electrode (11), a moving electrode (20) made of a semiconductor and displaceable in the thickness direction of the first silicon substrate (10) is disposed apart from and facing the first silicon substrate (10). An applied acceleration is detected on the basis of capacitance changes between the moving electrode (20) and the face of the first silicon substrate (10) accompanying displacement of the moving electrode (20). A space and an electrically insulative insulating layer (13) having a relative permittivity larger than that of air are interposed between the moving electrode (20) and the face of the first silicon substrate (10), side by side in the direction in which the moving electrode (20) and the first silicon substrate (10) are apart.

摘要翻译： 在半导体加速度传感器（S1）中，在由半导体制成并用作固定电极（11）的第一硅衬底（10）的一侧上方，由半导体制成的可移动的厚度的移动电极（20） 第一硅衬底（10）的方向与第一硅衬底（10）分开并面对第一硅衬底（10）。 基于移动电极（20）与伴随移动电极（20）移动的第一硅衬底（10）的面之间的电容变化来检测施加的加速度。 具有相对介电常数大于空气的空间和绝缘绝缘层（13）被插入到移动电极（20）和第一硅衬底（10）的表面之间，并且 移动电极（20）和第一硅衬底（10）分开。

公开(公告)号：US06973829B2

公开(公告)日：2005-12-13

申请号：US09925021

申请日：2001-08-09

申请人： Minekazu Sakai ,  Yoshiyuki Kato ,  Minoru Murata

发明人： Minekazu Sakai ,  Yoshiyuki Kato ,  Minoru Murata

IPC分类号： G01P15/125

CPC分类号： G01P15/125 ,  G01P2015/0814

摘要： A semiconductor dynamic quantity sensor has a support substrate with a rectangular opening portion, and a movable electrode and fixed electrodes are respectively supported by the support substrate through supporting portions to face the opening portion. The supporting portions supporting the movable electrode are arranged in a direction approximately the same as that in which the supporting portions supporting the fixed electrodes are arranged.

摘要翻译： 半导体动态量传感器具有矩形开口部分的支撑基板，并且可动电极和固定电极分别由支撑基板通过支撑部分支撑以面对开口部分。 支撑可动电极的支撑部分布置在与支撑固定电极的支撑部分布置的方向大致相同的方向上。

公开(公告)号：US20050263838A1

公开(公告)日：2005-12-01

申请号：US11137435

申请日：2005-05-26

申请人： Minekazu Sakai

发明人： Minekazu Sakai

IPC分类号： G01P21/00 ,  B81B7/02 ,  G01P15/125 ,  H01L29/84

CPC分类号： G01P15/125

摘要： When movable electrodes of beam arrangement structures are displaced in a direction perpendicular to the surface of a support substrate in first and second capacitance constituent portions by action of an acceleration while carrier voltages are applied, the difference between a first capacitance and second capacitance is output from the support substrate through a third capacitance constituent portion. Under self-diagnosis, the voltage applying counter electrode portion of the self-diagnosis fixed capacitance constituent portion is set to a first potential, and a signal output counter electrode portion of the third capacitance constituent portion is set to a second potential different from the first potential, whereby the potential of the support substrate corresponding to the fixed electrode in the first and second capacitance constituent portions is forcedly changed.

摘要翻译： 当施加载波电压时，通过加速度的作用，在布置结构的可移动电极在第一和第二电容构成部分的垂直于支撑基板的表面的方向上位移时，第一电容和第二电容之间的差从 支撑基板通过第三电容构成部分。 在自诊断下，将自诊断固定电容构成部分的电压施加对电极部分设定为第一电位，将第三电容构成部分的信号输出对置电极部分设定为与第一电位不同的第二电位 电位，由此强制地改变与第一和第二电容构成部分中的固定电极相对应的支撑衬底的电位。

公开(公告)号：US20050076714A1

公开(公告)日：2005-04-14

申请号：US10926147

申请日：2004-08-26

申请人： Minekazu Sakai ,  Tameharu Ohta

发明人： Minekazu Sakai ,  Tameharu Ohta

IPC分类号： G01P15/08 ,  G01P15/125 ,  G01P15/00

CPC分类号： G01P15/0802 ,  G01P15/125

摘要： An acceleration sensor is formed on a top surface of a laminated silicon-on-insulator substrate. The acceleration sensor is composed of first and second capacitors each including a movable electrode that moves according to acceleration imposed thereon. The first and the second capacitors are so made that their capacitances change differently when the same acceleration is imposed and that the capacitance difference represents an amount of acceleration imposed thereon. A third capacitor having an output electrode solidly connected to the base substrate via the insulation layer is also formed on the same silicon-on-insulator substrate. An output representing amount of acceleration is taken out from the output electrode of the third capacitor.

摘要翻译： 加速度传感器形成在层叠绝缘体上硅衬底的顶表面上。 加速度传感器由第一和第二电容器组成，每个电容器包括根据施加的加速度移动的可动电极。 第一和第二电容器被制成使得当施加相同的加速度时，其电容变化不同，并且电容差表示施加的加速度量。 具有通过绝缘层与基底基板牢固地连接的输出电极的第三电容器也形成在同一绝缘体上的衬底上。 从第三电容器的输出电极取出表示加速度的输出。

公开(公告)号：US06508126B2

公开(公告)日：2003-01-21

申请号：US09897016

申请日：2001-07-03

申请人： Minekazu Sakai ,  Seiki Aoyama ,  Hirotsugu Funato

发明人： Minekazu Sakai ,  Seiki Aoyama ,  Hirotsugu Funato

IPC分类号： G01P15125

CPC分类号： G01P15/0802 ,  G01P15/125 ,  G01P21/00 ,  G01P2015/0814

摘要： A dynamic quantity sensor has a weigh portion that is supported by a base portion to be displaced by a dynamic quantity, a movable electrode protruding from the weigh portion, and a fixed electrode protruding from the base portion and defining a detection interval with the movable electrode. The detection interval changes in response to displacement of the weight portion for detecting the dynamic quantity. Each of the movable electrode and the fixed electrode has a tapered plane shape with a width that decreases from a root portion toward a tip portion thereof.

公开(公告)号：US06388279B1

公开(公告)日：2002-05-14

申请号：US09095131

申请日：1998-06-10

申请人： Minekazu Sakai ,  Toshimasa Yamamoto ,  Yasutoshi Suzuki ,  Kenichi Yokoyama ,  Masakazu Terada ,  Eishi Kawasaki ,  Inao Toyoda

发明人： Minekazu Sakai ,  Toshimasa Yamamoto ,  Yasutoshi Suzuki ,  Kenichi Yokoyama ,  Masakazu Terada ,  Eishi Kawasaki ,  Inao Toyoda

IPC分类号： H01L2720

CPC分类号： G01L9/0054 ,  B81C1/00357 ,  B81C2201/019 ,  G01L9/0042

摘要： In the method for manufacturing a semiconductor substrate, a concavity and a connecting hole for connecting the concavity to the outside are formed on a lower face side of a first substrate, and the first substrate is laminated with a second substrate in an atmosphere at atmospheric pressure. A diaphragm is formed by thinning the first substrate from its upper face by polishing. A sealing hole reaching to the connecting hole is formed from the upper face of the first substrate. An oxide film is formed in the sealing hole in a vacuum, whereby the connecting hole is sealed while the pressure of the pressure reference chamber is reduced to a vacuum. In this way, since the pressure reference chamber is pressure-reduced in a final stage, the diaphragm can be prevented from deforming due to pressure difference during polishing.

摘要翻译： 在半导体衬底的制造方法中，在第一衬底的下表面上形成用于将凹部连接到外部的凹部和连接孔，并且将第一衬底与大气压的气氛中的第二衬底层叠 。 通过抛光使第一基板从其上表面变薄而形成隔膜。 从第一基板的上表面形成到达连接孔的密封孔。 在真空中在密封孔中形成氧化膜，由此在压力基准室的压力降低到真空的同时密封连接孔。 以这种方式，由于压力基准室在最终阶段被减压，所以可以防止由于研磨过程中的压力差导致的隔膜变形。

公开(公告)号：US06373093B1

公开(公告)日：2002-04-16

申请号：US09776769

申请日：2001-02-06

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L2976

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

公开(公告)号：US6020618A

公开(公告)日：2000-02-01

申请号：US758259

申请日：1996-11-27

申请人： Minekazu Sakai

发明人： Minekazu Sakai

IPC分类号： H01L21/3063 ,  H01L29/82 ,  H01L29/06

CPC分类号： H01L21/3063

摘要： A semiconductor device such as a semiconductor dynamic sensor which is produced at an improved chip yield is provided. Etching wiring having a main line and a branch line is formed on a chip region via an intervening insulating film. The chip region contains an N-type reduced thickness region and is surrounded by a P-type chip isolating layer. The etching wiring is formed with a gap (an etching wiring gap) from other etching wiring members or circuit wiring formed on the chip region via an intervening insulating film. The etching wiring gap is greater than any of the gaps between members of the circuit wiring.

摘要翻译： 提供了以提高的芯片产量生产的诸如半导体动态传感器的半导体器件。 通过中间绝缘膜在芯片区域上形成具有主线和分支线的蚀刻布线。 芯片区域包含N型缩小厚度的区域，被P型芯片隔离层包围。 蚀刻布线形成有与其它蚀刻布线构件或通过中间绝缘膜形成在芯片区域上的电路布线的间隙（蚀刻布线间隙）。 蚀刻布线间隙大于电路布线的构件之间的任何间隙。

公开(公告)号：US5063423A

公开(公告)日：1991-11-05

申请号：US567760

申请日：1990-08-15

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/7883

摘要： A tunnel insulating film of a three-layer structure, wherein an oxide film is interposed between nitrided oxide films, is formed on the surface of a semiconductor substrate. A first polysilicon film serving as a low-concentration impurity region is formed on the tunnel insulating film. An oxide film is formed on that region of the first polysilicon film, which corresponds to the tunnel insulating film, the oxide film having such a thickness that the film can serve as a stopper for impurity diffusion and can allow electrons to pass through. A second polysilicon film, having an impurity concentration higher than that of the first polysilicon film, is formed on the oxide film. The first and second polysilicon films constitute a floating gate. A third polysilicon film serving as a control gate is formed above the second polysilicon film, with an insulating layer interposed therebetween.

摘要翻译： 在半导体衬底的表面上形成三层结构的隧道绝缘膜，其中在氮化氧化物膜之间插入氧化膜。 在隧道绝缘膜上形成用作低浓度杂质区的第一多晶硅膜。 在第一多晶硅膜的与隧道绝缘膜相对应的区域上形成氧化膜，氧化膜具有使膜能够作为用于杂质扩散的阻挡层的厚度，并且可以使电子通过。 在氧化膜上形成杂质浓度高于第一多晶硅膜的第二多晶硅膜。 第一和第二多晶硅膜构成浮栅。 用作控制栅极的第三多晶硅膜形成在第二多晶硅膜上方，绝缘层位于其间。

公开(公告)号：US5017979A

公开(公告)日：1991-05-21

申请号：US344605

申请日：1989-04-28

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

摘要翻译： 在半导体衬底的表面上形成栅极氧化膜。 在对应于隧道区域的部分中形成厚度小于栅极绝缘膜厚度的隧道绝缘膜。 在栅极绝缘膜上形成杂质浓度低的第一硅膜。 在第一硅膜上形成杂质浓度高于第一硅膜的第二硅膜，以便与第一硅膜连接。 通过绝缘膜在第二硅膜上形成第三硅膜。 第二和第三硅膜分别形成浮动和控制栅极，从而形成半导体存储器件。