公开(公告)号：US20200349988A1

公开(公告)日：2020-11-05

申请号：US16837368

申请日：2020-04-01

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: G11C7/22 ,  G11C7/10 ,  G01R31/317 ,  G01R31/3177 ,  H04L12/26

Abstract: A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T1 . . . T6 at which the signals are allowed to change logical state, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein, irrespective of the data packet content: at each time stamp T1 . . . T6 exactly one of the signals changes logical state; each signal changes logical state twice during the cycle; and in the first half of the cycle, all signals change from a logical low state to a logical high state or all signals change from a logical high state to a logical low state.

公开(公告)号：US20200341937A1

公开(公告)日：2020-10-29

申请号：US16848223

申请日：2020-04-14

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Ling Wang ,  Michael Zimin

IPC: G06F13/42

Abstract: The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC.

公开(公告)号：US10670699B2

公开(公告)日：2020-06-02

申请号：US15697827

申请日：2017-09-07

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Abdellatif Zanati

IPC: G01S7/40 ,  G01S7/35 ,  G01S13/931 ,  G01S13/58

Abstract: Embodiments are provided for a radar device and a method for operating a radar device, the radar device having a transmitter and a receiver, the method including: generating a noise signal; mixing the noise signal with a transmitter output radio frequency (RF) signal to produce an intermediate signal, wherein the transmitter output RF signal is a version of a local oscillator (LO) signal having linearly increasing frequency; attenuating the intermediate signal to produce a test signal; adding the test signal to a receiver input RF signal to produce a combined receiver input RF signal; downmixing an amplified version of the combined receiver input RF signal with the LO signal to produce a combined low frequency signal; and correlating the combined low frequency signal with the noise signal to produce an error detection signal.

公开(公告)号：US10591536B1

公开(公告)日：2020-03-17

申请号：US16201396

申请日：2018-11-27

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: G01R31/28 ,  G01R31/3161 ,  G01R31/316 ,  H03M1/10

Abstract: An apparatus includes a linear analog circuit and data-check circuit. The linear analog circuit receives analog input signals and provides processed analog output signals. The linear analog circuit includes voltage-changing and voltage-impedance circuitry that perform processing of the analog input signals by the linear analog circuit and an analog test bus circuit (ATB) that selectively passes different ones of a plurality of input ports to at least one output port. A data-check circuit is communicatively coupled to the ATB and includes a data-processing circuit that detects an error conveyed by the linear analog circuit by applying a control signal, while the linear analog circuit and the data-check circuit facilitate testing of the linear analog circuit, to cause the ATB to selectively pass the different ones of the plurality of input ports.

公开(公告)号：US20200049756A1

公开(公告)日：2020-02-13

申请号：US16059547

申请日：2018-08-09

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Abdellatif Zanati

IPC: G01R31/14 ,  G01R31/18 ,  G01R31/28

Abstract: An example method includes stressing, under different circuit-stress test conditions, a plurality of different types of regional circuits susceptible to time dependent dielectric breakdown (TDDB), and in response, monitoring for levels of reliability failure associated with the plurality of different types of regional circuits. The method includes storing a set of stress-test data based on each of the levels of reliability failure, the set of stress-test data being stored within the integrated circuit to indicate reliability-threshold test data specific to the integrated circuit. Within the integrated circuit, an on-chip monitoring circuit indicates operational conditions of suspect reliability associated with dielectric breakdown of at least one of the plurality of different types of regional circuits. And, the method further includes, during operation of the integrated circuit, adjusting at least one of the different circuit-stress test conditions based on the indicated operational conditions of suspect reliability.

公开(公告)号：US20200031312A1

公开(公告)日：2020-01-30

申请号：US16044066

申请日：2018-07-24

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Michael Johannes Döscher ,  Abdellatif Zanati

IPC: B60R25/102 ,  B60R25/10 ,  B60R25/33 ,  B60R25/32 ,  G01C21/30

Abstract: A method includes generating a target map indicative of objects around the vehicle using sensor data from sensor circuitry of the vehicle, the sensor circuitry including at least one radar sensor; and determining, by processing circuitry, if the vehicle is being towed away. Determining if the vehicle is being towed away can include comparing the target map to a previously obtained target map, determining if the vehicle is moving based on the comparison, and in response to determining the vehicle is moving, outputting an alarm message indicative of the vehicle being towed away.

公开(公告)号：US20190383883A1

公开(公告)日：2019-12-19

申请号：US16009836

申请日：2018-06-15

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: G01R31/40 ,  G05F1/625 ,  G01R31/3177

Abstract: An apparatus embodiment includes a voltage regulator circuit that provides a regulated voltage supply signal, logic state circuitry, test control circuitry, and a supply-signal monitoring circuit. The logic state circuitry includes logic modules that are reconfigured between application controlled self-test modes in which data is shifted through the logic module and while being powered from the regulated voltage supply signal. The test control circuitry operates the controlled self-test mode by causing a predetermined set of the data to shift through the logic modules and that causes the logic state circuitry to load the voltage regulator circuit by stressing the voltage regulator circuit. The supply-signal monitoring circuit monitors a quality parameter of the regulated voltage supply signal and provides an indication of characteristics of the regulated voltage supply signal which bear on a likelihood that the voltage regulator circuit is associated with defective circuitry.

公开(公告)号：US20190377868A1

公开(公告)日：2019-12-12

申请号：US16004521

申请日：2018-06-11

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Michael Johannes Döscher

IPC: G06F21/55 ,  G01R31/3185 ,  G06F21/76

Abstract: Certain aspects of the disclosure are directed to methods and apparatuses of intrusion detection for integrated circuits. An example apparatus can include a wired communications bus configured and arranged to carry data and a plurality of integrated circuits. The plurality of integrated circuits can include a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits. The plurality of integrated circuits can further include a second integrated circuit configured and arranged to operate in a mission mode and supervise data traffic by monitoring communications including data patterns and accesses on the wired communications bus. In response to identifying a suspected illegitimate access, the second integrated circuit can perform a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits.

公开(公告)号：US10425068B1

公开(公告)日：2019-09-24

申请号：US16008544

申请日：2018-06-14

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: H03K3/84 ,  G01R31/3167 ,  G05F1/46 ,  H03F3/45

Abstract: A method embodiment includes combining a control signal of a voltage regulator circuit of an apparatus with pseudo-random noise, and using the control signal to provide an output voltage signal as attenuated by a power supply rejection ratio (PSRR) of an analog mixed-signal (AMS) circuit of the apparatus. The method further includes self-testing the AMS circuit by cross-correlating a signal indicative of the output voltage signal from the AMS circuit with the pseudo-random noise and, in response, assessing the results of the cross-correlation relative to a known threshold indicative of a performance level of the AMS circuit.

公开(公告)号：US20190187204A1

公开(公告)日：2019-06-20

申请号：US16176372

申请日：2018-10-31

Applicant: NXP B.V

Inventor： Michael Doescher ,  Jan-Peter Schat

IPC: G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3016

Abstract: An apparatus comprising: a functional circuit comprising one or more circuit components configured to perform a function based on one or more first input signals; at least one failure-prediction circuit for use in predicting failure of the functional circuit, the failure-prediction circuit comprising a replica of the functional circuit in terms of constituent circuit components; wherein the failure-prediction circuit is configured to be more susceptible to failure than said functional circuit, wherein the apparatus is configured to provide a prediction of failure of the functional circuit based on a determination of failure of the failure-prediction circuit.