公开(公告)号：US07067852B1

公开(公告)日：2006-06-27

申请号：US09660386

申请日：2000-09-12

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Manuel Carneiro

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Manuel Carneiro

IPC分类号： H01L29/74 ,  H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/86 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The ESD protection structure also includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structure also includes first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively.

摘要翻译： ESD保护结构包括第一导电类型的半导体衬底和设置在衬底中的第二导电类型的第一和第二阱区。 第一和第二阱区域被衬底的间隙区域分开。 还包括设置在与间隙区域相邻的第一和第二阱区域中的第一和第二浮动区域（第二导电类型）。 ESD保护结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区分开的第一导电类型的第一和第二接触区域。 ESD保护结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区隔开的第二导电类型的第一和第二接触区域。

公开(公告)号：US07064397B1

公开(公告)日：2006-06-20

申请号：US10649989

申请日：2003-08-27

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Ann Concannon ,  Marcel Ter Beek

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Ann Concannon ,  Marcel Ter Beek

IPC分类号： H01L29/76

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.

摘要翻译： 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过在PNP晶体管的发射极和集电极之间形成NPN晶体管的集电极而大大减小。

公开(公告)号：US07037814B1

公开(公告)日：2006-05-02

申请号：US10683858

申请日：2003-10-10

申请人： Vladislav Vashchenko ,  Andy Strachan ,  Peter J. Hopper ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Andy Strachan ,  Peter J. Hopper ,  Philipp Lindorfer

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L22/14 ,  H01L21/26513

摘要： In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the mask. The diffusion of dopant is completed by making use of an annealing stage.

摘要翻译： 在集成电路中，通过使用穿孔掩模来调整掺杂剂浓度水平。 跨越集成电路的不同区域的掺杂水平可以通过利用面罩中的穿孔的不同尺寸和间距而不同地限定。 通过使用退火阶段完成掺杂剂的扩散。

公开(公告)号：US07023029B1

公开(公告)日：2006-04-04

申请号：US10210943

申请日：2002-08-02

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

IPC分类号： H01L29/72

CPC分类号： H01L27/0262

摘要： In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.

摘要翻译： 在使用SCR类结构的ESD保护器件中，提供了高度鲁棒的垂直器件，并且容易地允许在制造期间调节触发电压。 此外，它可以基于PNP和NPN BJT结构的互补形式实现，以提供正脉冲和负脉冲保护。

公开(公告)号：US06963091B1

公开(公告)日：2005-11-08

申请号：US10743845

申请日：2003-12-22

申请人： Vladislav Vashchenko ,  Michael Mian ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Michael Mian ,  Peter J. Hopper

IPC分类号： H01L27/06 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/66984 ,  H01L27/0623 ,  H01L29/456

摘要： Spin-based microelectronic devices can be realized by utilizing ferromagnetic structures that make good ohmic contact with silicon, in order to avoid the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on silicon substrates, which are well-known and used in the industry. Thin layers of metal silicide, such as CoSi2 and NiSi2, are used as an intermediate layer between ferromagnetic contacts, such as cobalt and nickel contacts, and the silicon substrate. The thin silicide layers provide good ohmic contact between the ferromagnetic contacts and silicon, such that spin-polarized carriers can be injected into the silicon, and detected out of the silicon, without loss of spin polarization.

摘要翻译： 可以通过利用与硅进行良好的欧姆接触的铁磁结构来实现基于旋转的微电子器件，以避免肖特基势垒问题困扰现有的基于旋转的微电子学方法，同时允许器件基于硅衬底 闻名于世的行业。 金属硅化物的薄层，例如CoSi 2和NiSi 2，被用作铁磁性触点（例如钴和镍触点）和硅衬底之间的中间层。 薄硅化物层在铁磁触点和硅之间提供良好的欧姆接触，使得自旋极化载流子可以注入硅中，并从硅中检测出，而不损失自旋极化。

公开(公告)号：US06862216B1

公开(公告)日：2005-03-01

申请号：US10880176

申请日：2004-06-29

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/861 ,  G11C16/06

CPC分类号： G11C16/0416 ,  H01L29/7881 ,  H01L29/8616

摘要： A non-volatile memory cell including a gated diode and a single readout transistor, methods for programming and reading out such a cell, and a memory including an array of such cells. The readout transistor is an MOS transistor. The transistor and gated diode are formed in a volume of semiconductor material of one type, and share a source region, a control gate, and a floating gate. The transistor has a drain region formed of semiconductor material of one type and the diode has a drain region formed of semiconductor material of the opposite type.

摘要翻译： 包括门控二极管和单个读出晶体管的非易失性存储单元，用于编程和读出这样的单元的方法以及包括这种单元阵列的存储器。 读出晶体管是MOS晶体管。 晶体管和门控二极管形成为一种类型的半导体材料的体积，并且共享源极区域，控制栅极和浮动栅极。 晶体管具有由一种类型的半导体材料形成的漏极区域，并且二极管具有由相反类型的半导体材料形成的漏极区域。

公开(公告)号：US06855968B1

公开(公告)日：2005-02-15

申请号：US10356423

申请日：2003-01-30

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko

IPC分类号： H01L27/148 ,  H01L31/0224 ,  H01L31/09

CPC分类号： H01L31/0224 ,  H01L31/08 ,  H01L31/09

摘要： A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed below of the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in magnetic flux of the inductor.

摘要翻译： 能够检测千兆赫兹光信号的光子检测器利用形成在电感线圈下方的光子材料层。 当脉冲光源被施加到光子材料层时，光子材料产生改变电感器的磁通量的涡流。 然后可以通过检测电感器的磁通量的变化来检测信号。

公开(公告)号：US06853053B1

公开(公告)日：2005-02-08

申请号：US10436560

申请日：2003-05-12

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

IPC分类号： H01L27/02 ,  H01L31/11

CPC分类号： H01L27/0259

摘要： In a BJT ESD protection structure, the ESD current density is stabilized by partially blocking one or more of the emitter and n+ collector, sinker, and n-buried layer to define a comb-like structure for the partially blocked regions.

摘要翻译： 在BJT ESD保护结构中，ESD电流密度通过部分地阻挡发射极和n +集电极，沉没片和n埋层中的一个或多个来稳定，以限定部分阻挡区域的梳状结构。

公开(公告)号：US06852562B1

公开(公告)日：2005-02-08

申请号：US10728612

申请日：2003-12-05

申请人： Peter J. Hopper ,  Robert Drury ,  Philipp Lindorfer ,  Vladislav Vashchenko

发明人： Peter J. Hopper ,  Robert Drury ,  Philipp Lindorfer ,  Vladislav Vashchenko

IPC分类号： H01L21/00 ,  H01L27/146

CPC分类号： H01L27/14643 ,  H01L27/1462 ,  H01L27/14687

摘要： A color imager, which has a plurality of photodiodes, utilizes a layer of metal that is formed over the photodiodes. The metal layer has a plurality of different sized openings that lie vertically over the photodiodes to physically diffract, and thereby filter, the incident light that strikes the color imager.

摘要翻译： 具有多个光电二极管的彩色成像器利用形成在光电二极管上的金属层。 金属层具有多个不同尺寸的开口，其垂直地位于光电二极管上以物理衍射，从而过滤入射到彩色成像器的入射光。

公开(公告)号：US06844585B1

公开(公告)日：2005-01-18

申请号：US10173911

申请日：2002-06-17

申请人： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

发明人： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

IPC分类号： H01L21/265 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/788

CPC分类号： H01L21/26586 ,  H01L21/2652 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847

摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.

摘要翻译： 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。