公开(公告)号：US07714355B1

公开(公告)日：2010-05-11

申请号：US11312704

申请日：2005-12-20

Applicant: Vladislav Vashchenko ,  Alexei Sadovnikov ,  Peter J. Hopper ,  Andy Strachan

Inventor： Vladislav Vashchenko ,  Alexei Sadovnikov ,  Peter J. Hopper ,  Andy Strachan

IPC: H01L29/74

CPC classification number: H01L29/7322 ,  H01L29/0821 ,  H01L29/74

Abstract: In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.

Abstract translation: 在BSCR或BJT ESD钳位中，通过屏蔽收集器的一部分来控制BJT器件的集电极的尺寸来控制击穿电压和直流电压公差。

公开(公告)号：US20090206865A1

公开(公告)日：2009-08-20

申请号：US12212289

申请日：2008-09-17

Applicant: Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

Inventor： Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

IPC: G01R31/26 ,  H01L23/58

CPC classification number: G01R31/2623 ,  G01R31/2639 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled.

Abstract translation: 提供了一种测试结构和测试方法，用于表征在半导体集成电路中沿着深沟槽隔离结构的侧壁从P型有源区流向P型衬底的寄生PFET漏电流中的时间依赖性漂移 结构体。 深沟槽隔离结构的电容耦合特性用于通过使用形成为深沟槽结构的一部分的大的辅助沟槽网状网来控制深沟槽结构的电“偏置”。 沟槽网状网络可以靠近Vdd环或接地环放置，然后通过使用比例的电容分压网络，可以控制沟槽处的电位。

公开(公告)号：US07298159B1

公开(公告)日：2007-11-20

申请号：US11176994

申请日：2005-07-07

Applicant: Lisa V. Rozario ,  Andy Strachan

Inventor： Lisa V. Rozario ,  Andy Strachan

IPC: G01R31/26 ,  G01R31/00

CPC classification number: G01R31/2623

Abstract: The trench leakage current of a deep trench isolation structure is measured. The deep trench isolation structure, which is filled with polysilicon, contacts both a first region of a first conductivity type and a second region of a second conductivity type, and is proximate to a third region of the first conductivity type formed in the second region. Test voltages are applied to the structures and the leakage current is measured.

Abstract translation: 测量深沟槽隔离结构的沟槽漏电流。 填充有多晶硅的深沟槽隔离结构与第一导电类型的第一区域和第二导电类型的第二区域接触，并且接近形成在第二区域中的第一导电类型的第三区域。 对结构施加测试电压，并测量泄漏电流。

公开(公告)号：US07238553B1

公开(公告)日：2007-07-03

申请号：US11134911

申请日：2005-05-23

Applicant: Vladislav Vashchenko ,  Andy Strachan ,  Peter J. Hopper ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Andy Strachan ,  Peter J. Hopper ,  Philipp Lindorfer

IPC: H01L21/332

CPC classification number: H01L27/0248 ,  H01L29/7436

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.

Abstract translation: 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过形成一个晶体管的发射极，与另一个晶体管的下沉区域的尾部相邻。

公开(公告)号：US07105373B1

公开(公告)日：2006-09-12

申请号：US10640963

申请日：2003-08-14

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andy Strachan

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andy Strachan

IPC: H01L21/00

CPC classification number: H01L31/028 ,  H01L31/103 ,  Y02E10/547

Abstract: A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.

Abstract translation: 单结交叉光电二极管利用第一导电类型的交替的高度掺杂的第一区域和第二导电类型的高度掺杂的第二区域的堆叠，其在下面形成并接触第一区域以收集光子。 此外，第一导电类型的高掺杂沉降片接触每个第一区域，并且第二导电类型的高掺杂沉降片接触每个第二区域。

公开(公告)号：US06919588B1

公开(公告)日：2005-07-19

申请号：US10650000

申请日：2003-08-27

Applicant: Vladislav Vashchenko ,  Andy Strachan ,  Peter J. Hopper ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Andy Strachan ,  Peter J. Hopper ,  Philipp Lindorfer

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L29/7436

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.

Abstract translation: 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过形成一个晶体管的发射极，与另一个晶体管的下沉区域的尾部相邻。

公开(公告)号：US06639784B1

公开(公告)日：2003-10-28

申请号：US10283810

申请日：2002-10-30

Applicant: Peter Hopper ,  Philipp Lindorfer ,  Kyuwoon Hwang ,  Andy Strachan ,  Vladislav Vashchenko

Inventor： Peter Hopper ,  Philipp Lindorfer ,  Kyuwoon Hwang ,  Andy Strachan ,  Vladislav Vashchenko

IPC: H01J4228

CPC classification number: H01L28/91 ,  H01L27/0805

Abstract: A capacitor structure is formed in a wedge-shaped trench by forming alternating layers of insulating material and conductive material in the trench such that each layer of conductive material formed in the trench is electrically isolated from adjacent layers of conductive material formed in the trench. A first electrical contact is formed to electrically link in parallel a first set of alternating layers of conductive material. A second electrical contact is formed to electrically link in parallel a second set of alternating layers of conductive material. The two electrically isolated sets of inter-linked layers of conductive material define the interdigitated capacitor structure.

Abstract translation: 电容器结构通过在沟槽中形成绝缘材料和导电材料的交替层而形成在楔形沟槽中，使得形成在沟槽中的每个导电材料层与在沟槽中形成的导电材料的相邻层电隔离。 形成第一电接触以平行地电连接导电材料的第一组交替层。 形成第二电接触以平行地电连接第二组交替的导电材料层。 导电材料的两个电隔离的相互连接的层限定了交叉指向的电容器结构。

公开(公告)号：US07960998B2

公开(公告)日：2011-06-14

申请号：US12212289

申请日：2008-09-17

Applicant: Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

Inventor： Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

IPC: G01R31/02

CPC classification number: G01R31/2623 ,  G01R31/2639 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled.

Abstract translation: 提供了一种测试结构和测试方法，用于表征在半导体集成电路中沿着深沟槽隔离结构的侧壁从P型有源区流向P型衬底的寄生PFET漏电流中的时间依赖性漂移 结构体。 深沟槽隔离结构的电容耦合特性用于通过使用形成为深沟槽结构的一部分的大的辅助沟槽网状网来控制深沟槽结构的电“偏置”。 沟槽网状网络可以靠近Vdd环或接地环放置，然后通过使用比例的电容分压网络，可以控制沟槽处的电位。

公开(公告)号：US07488647B1

公开(公告)日：2009-02-10

申请号：US11201761

申请日：2005-08-11

Applicant: Charles A. Dark ,  Andy Strachan

Inventor： Charles A. Dark ,  Andy Strachan

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/4763

CPC classification number: H01L21/763 ,  H01L21/76202

Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.

Abstract translation: 公开了一种系统和方法，其防止在制造半导体器件时形成垂直鸟喙结构。 在半导体器件的衬底中形成多晶硅填充沟槽。 然后将一个或多个复合层施加在沟槽和衬底上。 然后施加掩模和蚀刻工艺以蚀刻与多晶硅填充沟槽相邻的复合层。 施加场氧化物工艺以在与沟槽相邻的衬底中形成场氧化物部分。 由于没有将场氧化物放置在沟槽上，所以没有形成垂直鸟的喙结构。 施加栅极氧化物层，并且在多晶硅填充的沟槽上形成保护帽，以保护沟槽免受后续处理步骤的不期望的影响。

公开(公告)号：US07192857B1

公开(公告)日：2007-03-20

申请号：US11109961

申请日：2005-04-20

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andy Strachan

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andy Strachan

IPC: H01L21/3205

CPC classification number: H01L29/41758 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.

Abstract translation: 功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。 电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。