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    RANK INTERLEAVING FOR SYSTEM META MODE OPERATIONS IN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) MEMORY DEVICE
    75.
    发明申请
    RANK INTERLEAVING FOR SYSTEM META MODE OPERATIONS IN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) MEMORY DEVICE 有权

    公开(公告)号：US20240402944A1

    公开(公告)日：2024-12-05

    申请号：US18495215

    申请日：2023-10-26

    Applicant: QUALCOMM Incorporated

    Inventor： Alain Artieri ,  Jungwon Suh ,  Subbarao Palacharla ,  Vikrant Kumar ,  Riccardo Iacobacci

    IPC: G06F3/06

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.

    MEMORY SYSTEM WITH ADAPTIVE REFRESH
    76.
    发明公开
    MEMORY SYSTEM WITH ADAPTIVE REFRESH 审中-公开

    公开(公告)号：US20240311317A1

    公开(公告)日：2024-09-19

    申请号：US18674138

    申请日：2024-05-24

    Applicant: QUALCOMM Incorporated

    Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

    IPC: G06F13/16

    CPC classification number: G06F13/1668

    Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

    Flexible dual ranks memory system to boost performance
    77.
    发明授权
    Flexible dual ranks memory system to boost performance 有权

    公开(公告)号：US11907141B1

    公开(公告)日：2024-02-20

    申请号：US17929946

    申请日：2022-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Subbarao Palacharla

    IPC: G06F13/16 ,  G06F12/06

    CPC classification number: G06F13/1694 ,  G06F12/0623

    Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

    Low power memory system using dual input-output voltage supplies
    78.
    发明授权
    Low power memory system using dual input-output voltage supplies 有权

    公开(公告)号：US11551730B2

    公开(公告)日：2023-01-10

    申请号：US17158485

    申请日：2021-01-26

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Joon Young Park ,  Mahalingam Nagarajan

    IPC: G11C5/02 ,  G11C5/14 ,  H03K7/02

    Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

    Low Power Memory System Using Dual Input-Output Voltage Supplies
    79.
    发明申请
    Low Power Memory System Using Dual Input-Output Voltage Supplies 有权

    公开(公告)号：US20220238142A1

    公开(公告)日：2022-07-28

    申请号：US17158485

    申请日：2021-01-26

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Joon Young Park ,  Mahalingam Nagarajan

    IPC: G11C5/14 ,  H03K7/02

    Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

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