公开(公告)号：US5246871A

公开(公告)日：1993-09-21

申请号：US805048

申请日：1991-12-11

Applicant: Raffaele Zambrano ,  Salvatore Musumeci ,  Salvatore Raciti

Inventor： Raffaele Zambrano ,  Salvatore Musumeci ,  Salvatore Raciti

IPC: H01L21/8248 ,  H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/8248 ,  Y10S148/126

Abstract: The problems normally linked to the creation of a power stage using BJT transistors are overcome realizing the power stage with BMFET transistors.

Abstract translation: 与使用BJT晶体管的功率级的创建通常相关的问题克服了实现具有BMFET晶体管的功率级。

公开(公告)号：US5013672A

公开(公告)日：1991-05-07

申请号：US259261

申请日：1988-10-18

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/033 ,  H01L21/762

CPC classification number: H01L21/033 ,  H01L21/76205 ,  H01L21/76216 ,  Y10S148/103

Abstract: The process calls for determination of the contact areas occupied by the collector, emitter and base implantations by selective removal of a layer of oxidation resistant material only from said contact areas and not from the separating zones between said areas.

公开(公告)号：US4965215A

公开(公告)日：1990-10-23

申请号：US287067

申请日：1988-12-21

Applicant: Raffaele Zambrano ,  Salvatore Musumeci

Inventor： Raffaele Zambrano ,  Salvatore Musumeci

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732

CPC classification number: H01L21/8222 ,  H01L21/761

Abstract: The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the emitter of the transistor of the integrated control circuit.

公开(公告)号：US4780430A

公开(公告)日：1988-10-25

申请号：US101430

申请日：1987-09-28

Applicant: Salvatore Musumeci ,  Raffaele Zambrano

Inventor： Salvatore Musumeci ,  Raffaele Zambrano

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L21/20

CPC classification number: H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/0823

Abstract: The invention concerns a process for formation of a high voltage monolithic semiconductor device that contains at least one power transistor and an integrated control circuit integrated in a single chip. The device is formed by means of a triple epitaxy which utilizes the same doping agent and by growth of the third epitaxial layer with a concentration of impurities greater than the previous ones. By spreading the buried layers till they penetrate inside the third epitaxial layer, collector regions of transistors in the integrated control circuit are obtained free of unwanted intermediate layers or phantom layers caused by the outdiffusion of doping substance present in the heavily doped isolation region with conductivity of the opposite type. Finally PN junctions are formed for the collector region of a power transistor and for the isolation zone of the integrated control circuit, capable of withstanding high voltages.

Abstract translation: 本发明涉及一种用于形成包含至少一个功率晶体管和集成在单个芯片中的集成控制电路的高电压单片半导体器件的工艺。 该器件通过三重外延形成，其利用相同的掺杂剂并且通过第三外延层的生长具有大于之前的杂质浓度。 通过扩展埋层，直到它们穿透第三外延层内部，获得集成控制电路中的晶体管的集电极区域，其不存在由重掺杂隔离区域中存在的掺杂物质的扩散引起的不需要的中间层或幻影层，导电性 相反的类型。 最后，为功率晶体管的集电极区域和能够承受高电压的集成控制电路的隔离区形成PN结。