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    COUPLED INDUCTOR SYSTEM HAVING MULTI-TAP COIL
    71.
    发明申请
    COUPLED INDUCTOR SYSTEM HAVING MULTI-TAP COIL 审中-公开
    具有多层线圈的耦合电感系统

    公开(公告)号：US20120242164A1

    公开(公告)日：2012-09-27

    申请号：US13430338

    申请日：2012-03-26

    申请人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith ,  Eric Blackall

    发明人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith ,  Eric Blackall

    IPC分类号： H01F38/14

    CPC分类号： H01F38/14 ,  H01F21/12

    摘要： Coupled inductor signal transfer systems are disclosed in which transmitter and receiver coils are inductively coupled in a configuration for wirelessly transferring power and/or data signals. In preferred implementations, the systems may be used for transmitting both power and data. Preferred embodiments of the invention have at least one multi-tap coil on the primary side and/or secondary side of the system. The selection of taps enables the effective size and/or number of coils to be dynamically changed according to operational needs.

    摘要翻译： 公开了耦合的电感信号传输系统，其中发射机和接收机线圈以用于无线传输功率和/或数据信号的配置感应耦合。 在优选实施方案中，系统可以用于发送功率和数据。 本发明的优选实施例在系统的初级侧和/或次级侧具有至少一个多抽头线圈。 抽头的选择使得能够根据操作需要动态地改变线圈的有效尺寸和/或数量。

    Non-volatile memory monitor
    73.
    发明授权
    Non-volatile memory monitor 有权
    非易失性存储器监视器

    公开(公告)号：US08102713B2

    公开(公告)日：2012-01-24

    申请号：US12492091

    申请日：2009-06-25

    申请人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith

    发明人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26

    摘要： The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to an evaluation state, monitoring for one or more particular characteristics, and returning to the normal operating state. Alternative embodiments of the invention are disclosed using various triggers and producing outputs capable of reporting or feeding back to influence the operation of the monitoring systems and methods, the NVM circuitry, or an external system. The invention includes an energy conservation feature, in that no power is consumed in the normal operating state, and low power in the evaluation state.

    摘要翻译： 本发明提供用于监视非易失性存储器（NVM）单元或NVM单元阵列的电路，系统和方法。 监视器能够从正常操作状态切换到评估状态，监视一个或多个特定特性，并返回到正常操作状态。 使用各种触发器公开本发明的替代实施例，并且产生能够报告或反馈以影响监视系统和方法，NVM电路或外部系统的操作的输出。 本发明包括节能特征，即在正常运行状态下不消耗功率，在评估状态下具有低功率。

    Non-Volatile Memory Monitor
    76.
    发明申请
    Non-Volatile Memory Monitor 有权
    非易失性内存监视器

    公开(公告)号：US20100027343A1

    公开(公告)日：2010-02-04

    申请号：US12492091

    申请日：2009-06-25

    申请人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith

    发明人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26

    摘要： The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to an evaluation state, monitoring for one or more particular characteristics, and returning to the normal operating state. Alternative embodiments of the invention are disclosed using various triggers and producing outputs capable of reporting or feeding back to influence the operation of the monitoring systems and methods, the NVM circuitry, or an external system. The invention includes an energy conservation feature, in that no power is consumed in the normal operating state, and low power in the evaluation state.

    摘要翻译： 本发明提供用于监视非易失性存储器（NVM）单元或NVM单元阵列的电路，系统和方法。 监视器能够从正常操作状态切换到评估状态，监视一个或多个特定特性，并返回到正常操作状态。 使用各种触发器公开本发明的替代实施例，并且产生能够报告或反馈以影响监视系统和方法，NVM电路或外部系统的操作的输出。 本发明包括节能特征，即在正常运行状态下不消耗功率，在评估状态下具有低功率。

    Method evaluating threshold level of a data cell in a memory device
    77.
    发明授权
    Method evaluating threshold level of a data cell in a memory device 有权
    方法评估存储器件中数据单元的阈值水平

    公开(公告)号：US07269528B2

    公开(公告)日：2007-09-11

    申请号：US11139172

    申请日：2005-05-28

    申请人： David John Baldwin ,  Eric Blackall ,  Joseph Devore ,  Ross E. Teggatz

    发明人： David John Baldwin ,  Eric Blackall ,  Joseph Devore ,  Ross E. Teggatz

    IPC分类号： G06F15/00

    CPC分类号： G11C16/34

    摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.

    摘要翻译： 一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特定的顺序：（1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

    System for oxide stress testing
    78.
    发明授权
    System for oxide stress testing 有权
    氧化物应力测试系统

    公开(公告)号：US06864702B1

    公开(公告)日：2005-03-08

    申请号：US10746984

    申请日：2003-12-24

    申请人： Ross E. Teggatz ,  Reed W. Adams ,  Suribhotla V. Rajasekhar

    发明人： Ross E. Teggatz ,  Reed W. Adams ,  Suribhotla V. Rajasekhar

    IPC分类号： G01R31/28 ,  G01R31/27

    CPC分类号： G01R31/2858

    摘要： The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure (400) that comprises a first transistor (406), having a first terminal coupled to ground, a second terminal coupled to a control signal (402), and a third terminal coupled to a first end of a first resistive element (412). A first voltage source (414) is coupled to the second end of the first resistive element. A second resistive element (416) is intercoupled between the second end of the first resistive element and ground. A second transistor (418) has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (420). A third resistive element (422) is intercoupled between the third terminal of the second transistor and ground; and a third transistor (424) has a first terminal coupled (426) to the oxide structure, a second terminal coupled to the first end of the first resistive elerment, and a third terminal coupled to a second voltage source (428).

    摘要翻译： 本发明提供了一种用于对氧化物结构进行应力测试以确定该结构在过应力条件下的可靠性的系统。 本发明提供了一种过应力测试结构（400），其包括第一晶体管（406），其具有耦合到地的第一端子，耦合到控制信号（402）的第二端子和耦合到控制信号 第一电阻元件（412）。 第一电压源（414）耦合到第一电阻元件的第二端。 第二电阻元件（416）在第一电阻元件的第二端和地之间相互配合。 第二晶体管（418）具有耦合到第一电阻元件的第二端的第一端子，耦合到第一电阻元件的第一端的第二端子和耦合到第一节点（420）的第三端子。 第三电阻元件（422）在第二晶体管的第三端与地之间相互耦合; 和第三晶体管（424）具有耦合到所述氧化物结构的第一端子（426），耦合到所述第一电阻器的第一端的第二端子和耦合到第二电压源（428）的第三端子。

    IC PMOS Schottky reverse bias protection structure
    79.
    发明授权
    IC PMOS Schottky reverse bias protection structure 有权
    IC PMOS肖特基反向偏置保护结构

    公开(公告)号：US06674621B2

    公开(公告)日：2004-01-06

    申请号：US09989066

    申请日：2001-11-21

    申请人： Alexander Noam Teutsch ,  Zbigniew Jan Lata ,  David John Baldwin ,  Ross E. Teggatz

    发明人： Alexander Noam Teutsch ,  Zbigniew Jan Lata ,  David John Baldwin ,  Ross E. Teggatz

    IPC分类号： F21V704

    CPC分类号： H01L27/0255 ,  H02H11/003

    摘要： The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

    摘要翻译： 本发明涉及一种反偏置保护结构，其包括具有漏极部分，栅极部分，源极部分和后栅极部分的PMOS晶体管结构，其中栅极部分耦合到第一电压电位，源极部分选择性地 可与电源连接，并且漏极部分选择性地耦合到需要从电源供给的电力的电路。 反向偏置保护结构还包括具有耦合到PMOS晶体管结构的源极部分的阳极的肖特基二极管结构以及耦合到PMOS结构的背栅极部分的阴极。 在正向偏置条件下，PMOS晶体管导通并呈现出小的电压降。 在反向偏置条件下，PMOS晶体管截止，肖特基结构反向偏置，从而防止电流通过保护结构。

    Auxiliary boundary regulator that provides enhanced transient response
    80.
    发明授权
    Auxiliary boundary regulator that provides enhanced transient response 有权
    辅助边界调节器，提供增强的瞬态响应

    公开(公告)号：US06650093B1

    公开(公告)日：2003-11-18

    申请号：US10162113

    申请日：2002-06-03

    申请人： Dave Baldwin ,  Sanmukh Patel ,  Ross E. Teggatz

    发明人： Dave Baldwin ,  Sanmukh Patel ,  Ross E. Teggatz

    IPC分类号： G05F1613

    CPC分类号： G05F1/613

    摘要： The regulator circuit with an auxiliary boundary regulator that provides enhanced transient response includes: an upper comparator 24 having a first input coupled to a feedback node and a second input coupled to a first reference voltage node V_HIGH; a lower comparator 26 having a first input coupled to the feedback node and a second input coupled to a second reference voltage node V_LOW; a first switching device 30 having a control node coupled to an output of the upper comparator 24; a second switching device 28 having a control node coupled to an output of the lower comparator 26; an inductor 36 having a first end coupled to the first and second switching devices 28 and 30, and a second end coupled to an output node Vout; and a feedback circuit 32 and 34 coupled between the output node Vout and the feedback node. This circuit provides a precise, quiet, linear regulator that provides a tightly regulated output with a fast regulator working in parallel to ensure that the output voltage stays within an acceptable boundary.

    摘要翻译： 具有提供增强的瞬态响应的辅助边界调节器的调节器电路包括：具有耦合到反馈节点的第一输入和耦合到第一参考电压节点V_HIGH的第二输入的上比较器24; 下比较器26具有耦合到反馈节点的第一输入和耦合到第二参考电压节点V_LOW的第二输入; 具有耦合到上比较器24的输出的控制节点的第一开关装置30; 具有耦合到下比较器26的输出的控制节点的第二开关装置28; 电感器36，其具有耦合到第一和第二开关器件28和30的第一端，以及耦合到输出节点Vout的第二端; 以及耦合在输出节点Vout和反馈节点之间的反馈电路32和34。 该电路提供了一个精确，安静的线性稳压器，提供紧密调节的输出，并具有并联工作的快速调节器，以确保输出电压保持在可接受的边界内。