公开(公告)号：US07554406B2

公开(公告)日：2009-06-30

申请号：US11695017

申请日：2007-03-31

申请人： Luca G. Fasoli ,  Ali K. Al-Shamma ,  Kenneth K. So

发明人： Luca G. Fasoli ,  Ali K. Al-Shamma ,  Kenneth K. So

IPC分类号： H03F3/60

CPC分类号： G11C7/067 ,  G11C7/02 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/18 ,  G11C8/14

摘要： An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

摘要翻译： 示例性放大器电路包括具有第一配置的第一组空间分布的最终放大器级和具有不同于第一配置的第二配置的第二组空间分布的最终放大器级。 两个组对于它们各自的最终放大器级共享相同的控制节点，并且两个组共享相同的放大器输出节点。 每个组通常在另一个被禁用的时间启用。 在结合存储器阵列的某些实施例中，只有一个关键的模拟节点必须被布置在整个存储器阵列中。

公开(公告)号：US20080238522A1

公开(公告)日：2008-10-02

申请号：US11695011

申请日：2007-03-31

申请人： Tyler J. Thorp ,  Luca G. Fasoli

发明人： Tyler J. Thorp ,  Luca G. Fasoli

IPC分类号： H03L5/00

CPC分类号： H03K3/356182

摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.

摘要翻译： 公开了用于电平移位对应于第一电压域的输入信号的电平移位电路，以产生对应于第二高电压域的一对互补输出信号。 用于高电压输出节点的放电电路中的反馈敏感器件被保护，而不管输出节点上的负载如何，并且不需要精确的晶体管尺寸作为输出负载的函数。 快速响应敏感器件由与敏感器件串联的电压转换器电路保护，以限制敏感器件上的电压，即使在最高输出电压下的高电容输出节点。 然后旁路电压移位器电路以提供完全到达下电源轨的输出低电平。

公开(公告)号：US07391638B2

公开(公告)日：2008-06-24

申请号：US11552426

申请日：2006-10-24

申请人： Luca G. Fasoli ,  Tyler Thorp

发明人： Luca G. Fasoli ,  Tyler Thorp

IPC分类号： G11C16/24

CPC分类号： G11C16/12

摘要： Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

摘要翻译： 公开了用于编程存储器件的存储器单元的改进的电路和方法。 改进的电路和方法用于保护存储器单元免受在编程存储器单元期间可能施加的潜在的有害电能。 此外，改进的电路和方法操作以检测何时已经实现了存储器单元的编程。 改进的电路和方法对于非易失性存储器单元的编程特别有用。 在一个实施例中，存储器件涉及半导体存储器产品，例如半导体存储器芯片或便携式存储卡。

公开(公告)号：US20080094916A1

公开(公告)日：2008-04-24

申请号：US11552472

申请日：2006-10-24

申请人： Luca G. Fasoli

发明人： Luca G. Fasoli

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C8/08 ,  G11C13/00 ,  G11C13/0028 ,  G11C13/0069 ,  G11C17/18 ,  G11C2013/0078

摘要： Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and methods can operate to ensure that programming of the memory cells is performed in a controlled manner using only a program current. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

摘要翻译： 公开了用于编程存储器件的存储器单元的改进的电路和方法。 改进的电路和方法操作以将存储器单元与可能在存储器单元的编程之前的预充电阶段期间施加的潜在的有害电能隔离。 此外，改进的电路和方法可以操作以确保仅使用程序电流以受控方式执行存储器单元的编程。 改进的电路和方法对于非易失性存储器单元的编程特别有用。 在一个实施例中，存储器件涉及半导体存储器产品，例如半导体存储器芯片或便携式存储卡。

公开(公告)号：US20080094892A1

公开(公告)日：2008-04-24

申请号：US11552441

申请日：2006-10-24

申请人： Luca G. Fasoli ,  Tyler Thorp

发明人： Luca G. Fasoli ,  Tyler Thorp

IPC分类号： G11C16/04

CPC分类号： G11C17/18 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3481 ,  G11C2211/5624 ,  G11C2211/5645 ,  G11C2213/32

摘要： Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

摘要翻译： 公开了用于编程存储器件的存储器单元的改进的电路和方法。 改进的电路和方法用于保护存储器单元免受在编程存储器单元期间可能施加的潜在的有害电能。 此外，改进的电路和方法操作以检测何时已经实现了存储器单元的编程。 改进的电路和方法对于非易失性存储器单元的编程特别有用。 在一个实施例中，存储器件涉及半导体存储器产品，例如半导体存储器芯片或便携式存储卡。

公开(公告)号：US20110096588A1

公开(公告)日：2011-04-28

申请号：US12606111

申请日：2009-10-26

申请人： Luca G. Fasoli

发明人： Luca G. Fasoli

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0011 ,  G11C2213/76 ,  G11C2213/79

摘要： A nonvolatile memory array architecture includes a resistive element between each common source/drain (intermediate) node and data line (or bit line), in an otherwise virtual ground-like memory array having serially-connected transistors coupled to the same word line. However, every N+1 transistors the corresponding resistive element is omitted (or generally kept in a low resistance state) to form transistor strings. This achieves an array density of 4F2*(N+1)/N, which approaches 4F2 array density for reasonable values of N. Such memory arrays are well suited for use in a three-dimensional memory array having distinct memory planes stacked above each other on multiple levels above a substrate.

摘要翻译： 非易失性存储器阵列架构包括在每个公共源极/漏极（中间）节点和数据线（或位线）之间的电阻元件，其中虚拟的地面状存储器阵列具有耦合到相同字线的串联连接的晶体管。 然而，每个N + 1个晶体管相应的电阻元件被省略（或通常保持在低电阻状态）以形成晶体管串。 这实现了阵列密度为4F2 *（N + 1）/ N，对于N的合理值，其接近4F2阵列密度。这种存储器阵列非常适合用于具有彼此层叠的不同存储器层的三维存储器阵列 在基底上的多个水平上。

公开(公告)号：US07696805B2

公开(公告)日：2010-04-13

申请号：US11695013

申请日：2007-03-31

申请人： Tyler J. Thorp ,  Luca G. Fasoli

发明人： Tyler J. Thorp ,  Luca G. Fasoli

IPC分类号： H03L5/00

CPC分类号： H03K3/35613

摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.

摘要翻译： 公开了用于电平移位对应于第一电压域的输入信号的电平移位电路，以产生对应于第二高电压域的一对互补输出信号。 用于高电压输出节点的放电电路中的反馈敏感器件被保护，而不管输出节点上的负载如何，并且不需要精确的晶体管尺寸作为输出负载的函数。 快速响应敏感器件由与敏感器件串联的电压转换器电路保护，以限制敏感器件上的电压，即使在最高输出电压下的高电容输出节点。 然后旁路电压移位器电路以提供完全到达下电源轨的输出低电平。

公开(公告)号：US07558140B2

公开(公告)日：2009-07-07

申请号：US11695015

申请日：2007-03-31

申请人： Luca G. Fasoli ,  Ali K. Al-Shamma ,  Kenneth K. So

发明人： Luca G. Fasoli ,  Ali K. Al-Shamma ,  Kenneth K. So

IPC分类号： G11C7/02

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/067 ,  G11C7/08 ,  G11C7/1042 ,  G11C7/1069 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

摘要： An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

摘要翻译： 示例性放大器电路包括具有第一配置的第一组空间分布的最终放大器级和具有不同于第一配置的第二配置的第二组空间分布的最终放大器级。 两个组对于它们各自的最终放大器级共享相同的控制节点，并且两个组共享相同的放大器输出节点。 每个组通常在另一个被禁用的时间启用。 在结合存储器阵列的某些实施例中，只有一个关键的模拟节点必须被布置在整个存储器阵列中。

公开(公告)号：US20080239839A1

公开(公告)日：2008-10-02

申请号：US11695015

申请日：2007-03-31

申请人： Luca G. Fasoli ,  Ali K. Al-Shamma ,  Kenneth K. So

发明人： Luca G. Fasoli ,  Ali K. Al-Shamma ,  Kenneth K. So

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/067 ,  G11C7/08 ,  G11C7/1042 ,  G11C7/1069 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

摘要： An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.

摘要翻译： 示例性放大器电路包括具有第一配置的第一组空间分布的最终放大器级和具有不同于第一配置的第二配置的第二组空间分布的最终放大器级。 两个组对于它们各自的最终放大器级共享相同的控制节点，并且两个组共享相同的放大器输出节点。 每个组通常在另一个被禁用的时间启用。 在结合存储器阵列的某些实施例中，只有一个关键的模拟节点必须被布置在整个存储器阵列中。