公开(公告)号：US20100199955A1

公开(公告)日：2010-08-12

申请号：US12367380

申请日：2009-02-06

申请人： Jeffrey P. Smith

发明人： Jeffrey P. Smith

IPC分类号： F02M31/20

CPC分类号： F02B29/0456 ,  F28D1/05366 ,  F28D2021/0082 ,  F28F9/0263 ,  F28F9/0278 ,  F28F9/0282 ,  Y02T10/146

摘要： A charge air cooler suitable for use in vehicles, such as Class 8 trucks, is disclosed. The charge air cooler includes one or more enhanced flow features that provide improved efficiency to an associated internal combustion engine. In one embodiment, the charge air cooler may include enhanced flow features that smooth the charge air flow as it transitions from an input plenum to the charge air tube conduits for reducing possible system pressure drop. In another embodiment, the input plenum and/or output plenum may be configured in order to maintain a constant charge air velocity across the inlet surface of the cooling core. To that end, the plenum may include a tapered lower section that decreases in width W, and thus, the cross sectional flow area into the cooling core, as the plenum extends from an upper region of the cooling core to the bottom of the cooling core.

摘要翻译： 公开了适用于诸如8类卡车的车辆的增压空气冷却器。 增压空气冷却器包括一个或多个增强的流动特征，其为相关联的内燃机提供改进的效率。 在一个实施例中，增压空气冷却器可以包括增强的流动特征，其在增压空气流从输入增压室转变到增压空气管导管时平滑加压空气流，以减少可能的系统压降。 在另一个实施例中，可以配置输入增压室和/或输出增压室，以便在冷却芯的入口表面上保持恒定的增压空气速度。 为此，气室可以包括锥形下部，其在宽度W上减小，因此，当冷​​凝芯从冷却芯的上部区域延伸到冷却芯的底部时，进入冷却芯的横截面流动区域 。

公开(公告)号：US06396109B1

公开(公告)日：2002-05-28

申请号：US09388943

申请日：1999-09-02

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L2976

CPC分类号： H01L21/8249

摘要： A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N− conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12). More particularly, the steps of forming the P conductivity type buried layer (30) may be performed a part of a simultaneous formation of a collector element of the PNP transistor (11) elsewhere on the substrate (12).

摘要翻译： 在BiCMOS工艺中制造隔离NMOS晶体管（10）的方法包括在P导电型半导体衬底（12）中形成N-导电型DUF层（19），随后形成交替的连续N +和P导电型掩埋区 （30,26）在衬底（12）中。 然后在衬底（12）上形成基本上本征的半导体材料层（32），其中分别在其上形成交替和连续的N和P导电类型阱（35,36）并延伸到N +和P导电类型埋置 地区（30,26）。 最后，NMOS源极和漏极区（48）形成在至少一个P导电型阱（35）中。 该方法优选与衬底（12）上的其它地方的双极晶体管结构（11）的构造同时进行。 更具体地，形成P导电型掩埋层（30）的步骤可以在衬底（12）上同时形成PNP晶体管（11）的集电极元件的其他部分的一部分。

公开(公告)号：US6033946A

公开(公告)日：2000-03-07

申请号：US761267

申请日：1996-12-06

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L21/8249 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/1087 ,  H01L21/8249 ,  H01L29/1083 ,  H01L29/78

摘要： A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12). More particularly, the steps of forming the P conductivity type buried layer (30) may be performed a part of a simultaneous formation of a collector element of the PNP transistor (11) elsewhere on the substrate (12).

摘要翻译： 在BiCMOS工艺中制造隔离NMOS晶体管（10）的方法包括在P导电型半导体衬底（12）中形成N-导电型DUF层（19），随后形成交替的连续N +和P导电型掩埋区 （30,26）在衬底（12）中。 然后在衬底（12）上形成基本上本征半导体材料层（32），其中分别在其上形成交替和连续的N和P导电类型阱（35,36）并且延伸到N +和P导电类型埋置 地区（30,26）。 最后，NMOS源极和漏极区（48）形成在至少一个P导电型阱（35）中。 该方法优选与衬底（12）上的其它地方的双极晶体管结构（11）的构造同时进行。 更具体地，形成P导电型掩埋层（30）的步骤可以在衬底（12）上同时形成PNP晶体管（11）的集电极元件的其他部分的一部分。

公开(公告)号：US5527722A

公开(公告)日：1996-06-18

申请号：US438119

申请日：1995-05-08

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0688 ,  H01L27/088 ,  H01L27/105

摘要： A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a.sub.1, 90b.sub.1) that are self-aligned with a gate (78) and N+ regions (90a.sub.2, 90b.sub.2) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-16d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.

摘要翻译： 半导体器件（76）设置有包括NMOS晶体管（78）和PMOS晶体管（82b）的高压部分和包括NMOS晶体管（80）和PMOS晶体管82（a）的低电压部分。 高压NMOS晶体管（78）包括具有与栅极（78）自对准的N区（90a1,90b1）和自我对准的N +区（90a2,90b2）的源/漏区（90a，90b） 与形成在栅极（78）的侧壁上的侧壁间隔物（91）对准，以提高连续高压操作条件下的可靠性。 低电压NMOS晶体管包括与侧壁间隔物（92）自对准的源极/漏极区域（92a，92b），以允许将沟道长度缩放到小于2微米。 低压PMOS晶体管（82a）和高电压PMOS晶体管（82b）包括源极/漏极区域（116a-16d），其与在侧壁间隔物（91）上形成的侧壁间隔物延伸区域（110a）自对准，允许低 电压PMOS晶体管沟道长度要缩放到小于2微米。

公开(公告)号：US4994887A

公开(公告)日：1991-02-19

申请号：US120558

申请日：1987-11-13

申请人： Louis N. Hutter ,  Mark E. Gibson ,  Jeffrey P. Smith ,  Shiu-Hang Yan ,  Arnold C. Conway ,  John P. Erdeljac ,  James D. Goon ,  AnhKim Duong ,  Mary A. Murphy ,  Susan S. Kearney

发明人： Louis N. Hutter ,  Mark E. Gibson ,  Jeffrey P. Smith ,  Shiu-Hang Yan ,  Arnold C. Conway ,  John P. Erdeljac ,  James D. Goon ,  AnhKim Duong ,  Mary A. Murphy ,  Susan S. Kearney

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L27/0623

摘要： An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.

摘要翻译： 描述了具有PMOS，NMOS和NPN晶体管的集成电路用于需要数字和模拟电路的应用。 该集成电路设计为允许在集成电路中使用标准CMOS单元，而无需重新设计。 提供了P +衬底（48），其上形成有第一P-外延层（46）。 分别为PMOS和NPN晶体管提供N + DUF区域（50,52）。 基部区域（68）通过注入和扩散形成在N阱（58）中。 在扩散之前，在基底（68）上形成氮化物层（70）以提供惰性退火。 基极扩散和集电极扩散发生在CMOS沟道停止和源极/漏极扩散之前，以防止改变MOS晶体管的扩散时间。