公开(公告)号：US06493801B2

公开(公告)日：2002-12-10

申请号：US09771098

申请日：2001-01-26

申请人： Simon C. Steely, Jr. ,  Nikolaos Hardavellas

发明人： Simon C. Steely, Jr. ,  Nikolaos Hardavellas

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F12/0804 ,  G06F12/0822

摘要： An adaptive cache coherent purging protocol includes recognizing system performance, especially latency, is affected by when cache is purged. The occurrence of performance enhancing and degrading events regarding a cache are counted and compared to a threshold. When the threshold is triggered the cache becomes a candidate for purging. In an embodiment, a time out delay is implemented before actual purging occurs. When the threshold is not triggered but a cache event occurs, a fake time out delay is triggered and the count is adaptively either raised, lowered or set to zero in response to performance enhancing and/or degrading events. The effect is to make the actual purging more likely if the history of cache events indicates that the performance would be enhanced thereby or less likely if the history indicates that the performance would be degraded thereby.

公开(公告)号：US06295585B1

公开(公告)日：2001-09-25

申请号：US08482925

申请日：1995-06-07

申请人： Richard B. Gillett, Jr. ,  Glenn P. Garvey ,  Simon C. Steely, Jr.

发明人： Richard B. Gillett, Jr. ,  Glenn P. Garvey ,  Simon C. Steely, Jr.

IPC分类号： G06F1314

CPC分类号： G06F9/544

摘要： A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item. If there is an error during the transmission of the message, the receiving node does not transmit an acknowledgement, and the sending node is thereby notified that an error has occurred.

摘要翻译： 多节点计算机网络包括通过数据链路耦合在一起的多个节点。 每个节点包括本地存储器，其还包括共享存储器。 要由节点共享的某些数据项存储在存储器的共享部分中。 与每个共享数据项相关联的是数据结构。 当与系统中的其他节点共享数据的节点寻求修改数据时，它将数据链路上的修改发送到网络中的其他节点。 群集中的每个节点按顺序接收每个更新。 作为修改节点的最后一次传输的一部分，向群集中的接收节点发送确认请求。 接收确认请求的每个节点向发送节点返回确认。 返回的确认被写入与共享数据项相关联的数据结构。 如果在消息的发送期间存在错误，则接收节点不发送确认，并且由此通知发送节点发生了错误。

公开(公告)号：US06249520B1

公开(公告)日：2001-06-19

申请号：US08957664

申请日：1997-10-24

申请人： Simon C. Steely, Jr. ,  Stephen R. VanDoren ,  Madhumitra Sharma ,  Craig D. Keefer ,  David W. Davis

发明人： Simon C. Steely, Jr. ,  Stephen R. VanDoren ,  Madhumitra Sharma ,  Craig D. Keefer ,  David W. Davis

IPC分类号： H04L1250

CPC分类号： G06F13/4022 ,  G06F12/0826 ,  G06F15/17393

摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.

摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

公开(公告)号：US06202126B1

公开(公告)日：2001-03-13

申请号：US08957697

申请日：1997-10-24

申请人： Stephen Van Doren ,  Simon C. Steely, Jr. ,  Madhumitra Sharma

发明人： Stephen Van Doren ,  Simon C. Steely, Jr. ,  Madhumitra Sharma

IPC分类号： G06F1200

CPC分类号： G06F12/0804 ,  G06F12/0833

摘要： A method for preventing inadvertent invalidation of data elements in a system having a separate probe queue and fill queue for each central processing unit, is provided wherein a central processing unit stores a clean data element, that would otherwise have been discarded, in a victim data buffer when it is evicted from cache. The central processing unit subsequently issues a clean-victim command to the system control logic when the readmiss or read-miss-modify command, targeting the data element that maps to the same location in cache as the clean data element, is issued. The clean-victim command causes the duplicate tag store to indicate that the clean data element is no longer stored in that central processing unit's cache. While the data is stored therein, the central processing unit cannot issue a probe message that targets that data until the victim data buffer has been deallocated. The central processing unit cannot modify the data element and therefore, if a probe invalidate has previously been issued for the clean version of the data element, it will not be able to inadvertently invalidate a modified version of the data element.

摘要翻译： 提供了一种用于防止在具有用于每个中央处理单元的单独的探测队列和填充队列的系统中的数据元素的无意的无效的方法，其中中央处理单元将干脆的数据元素（否则将被丢弃）存储在受害者数据中 缓冲区从缓存中逐出。 当发出针对映射到与清洁数据元素在高速缓存中的相同位置的数据元素的readmiss或read-miss-modify命令时，中央处理单元随后向系统控制逻辑发出清理受害者命令。 clean-victim命令使重复的标签存储指示干净的数据元素不再存储在该中央处理器的缓存中。 当数据存储在其中时，中央处理单元不能发出针对该数据的探测消息，直到受害者数据缓冲器被释放。 中央处理单元不能修改数据元素，因此如果先前为数据元素的干净版本发出了探针无效，则它将无法无意中使数据元素的修改版本无效。

公开(公告)号：US6108737A

公开(公告)日：2000-08-22

申请号：US957097

申请日：1997-10-24

申请人： Madhumitra Sharma ,  Stephen R. Van Doren ,  Kourosh Gharachorloo ,  Simon C. Steely, Jr.

发明人： Madhumitra Sharma ,  Stephen R. Van Doren ,  Kourosh Gharachorloo ,  Simon C. Steely, Jr.

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/30087 ,  G06F12/0828 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

摘要： A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memory reference operation. The commit-signal facilitates inter-reference ordering; moreover, the commit signal indicates the apparent completion of the memory reference operation, rather than actual completion of the operation. The apparent completion of an operation occurs substantially sooner than the actual completion of an operation, thereby improving performance of the multiprocessor system.

摘要翻译： 一种机制减少了具有共享存储器的多处理器系统中存储器参考操作的集合之间的参考间排序的等待时间。 该机制包括响应于发出的存储器参考操作而由多处理器系统的控制逻辑产生的提交信号。 提交信号促进参考间的排序; 此外，提交信号指示存储器参考操作的明显完成，而不是实际完成操作。 操作的明显完成大大早于实际完成操作，从而提高了多处理器系统的性能。

公开(公告)号：US6061765A

公开(公告)日：2000-05-09

申请号：US957505

申请日：1997-10-24

申请人： Stephen Van Doren ,  Simon C. Steely, Jr. ,  Robert Eugene Stewart ,  James Bernard Keller

发明人： Stephen Van Doren ,  Simon C. Steely, Jr. ,  Robert Eugene Stewart ,  James Bernard Keller

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0822

摘要： In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim data, using a set of victim data buffers coupled to a central processing unit of a computer system. Storage locations referred to as a "victim valid bit" and a "probe valid bit" are associated with each victim data buffer in the computer system to indicate a release condition for the coupled victim data buffer. With such an arrangement, the victim data buffer can be deallocated when the victim valid bit and the probe valid bit have both been cleared.

摘要翻译： 根据本发明，提供了一种方法和装置，用于存储从高速缓存中移出的受害者数据，并且使用耦合到计算机的中央处理单元的一组受害者数据缓冲器来满足目标受害者数据的待决请求或探测消息 系统。 称为“受害者有效位”的存储位置和“探测有效位”与计算机系统中的每个受害者数据缓冲器相关联，以指示耦合的受害者数据缓冲器的释放条件。 通过这样的配置，当受害者有效位和探测有效位都被清除时，可以释放受害者数据缓冲区。

公开(公告)号：US5758142A

公开(公告)日：1998-05-26

申请号：US251078

申请日：1994-05-31

申请人： Scott McFarling ,  Simon C. Steely, Jr. ,  Joel Emer ,  Edward McLellan

发明人： Scott McFarling ,  Simon C. Steely, Jr. ,  Joel Emer ,  Edward McLellan

IPC分类号： G06F9/38 ,  G06F9/22

CPC分类号： G06F9/30061 ,  G06F9/3848

摘要： A predictor which chooses between two or more predictors is described. The predictor includes a first component predictor which operates according to a first algorithm to produce a prediction of an action and a second component predictor which operates according to a second algorithm to produce a prediction of said action. The predictor also includes means, coupled to each of said first and second predictors, for choosing between predictions provided from said predictors to provide a prediction of the action from the predictor. The predictor can be used to predict outcomes of branches, cache hits, prefetched instruction sequences, and so forth.

摘要翻译： 描述了在两个或更多个预测器之间选择的预测器。 预测器包括第一分量预测器，其根据第一算法操作以产生动作的预测;以及第二分量预测器，其根据第二算法进行操作以产生所述动作的预测。 预测器还包括耦合到所述第一和第二预测器中的每一个的装置，用于在从所述预测器提供的预测之间进行选择以提供来自预测器的动作的预测。 预测器可用于预测分支的结果，缓存命中，预取指令序列等。