公开(公告)号：US20100115386A1

公开(公告)日：2010-05-06

申请号：US12631455

申请日：2009-12-04

申请人： Yuming Zhu ,  Manish Goel

发明人： Yuming Zhu ,  Manish Goel

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： H03M13/1111 ,  H04L1/0052 ,  H04L1/0057

摘要： A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

摘要翻译： 用于解码具有高子矩阵度的LDPC码的分层消息更新方法和系统具有可扩展的可折叠和灵活的解码器架构，以支持具有非常小的硬件开销和高吞吐量的任意高子矩阵度的LDPC码。 本发明的实施例支持具有子矩阵度数W => 1的LDPC码。

公开(公告)号：US07561618B2

公开(公告)日：2009-07-14

申请号：US11105755

申请日：2005-04-14

申请人： Antonio F. Mondragon-Torres ,  Steven P. Pekarich ,  Timothy M. Schmidl ,  Aris Papasakellariou ,  Anand G. Dabak ,  Eko N. Onggosanusi ,  Manish Goel

发明人： Antonio F. Mondragon-Torres ,  Steven P. Pekarich ,  Timothy M. Schmidl ,  Aris Papasakellariou ,  Anand G. Dabak ,  Eko N. Onggosanusi ,  Manish Goel

IPC分类号： H03H7/30

CPC分类号： H04L25/03019 ,  H04B1/7105 ,  H04B1/7117 ,  H04B7/0837 ,  H04L2025/03509 ,  H04L2025/03566 ,  H04L2025/03617

摘要： A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.

摘要翻译： 一种系统，包括适于耦合到多个接收天线的多个自适应均衡器，所述天线中的每一个能够接收多径延迟分布估计（MDPE），互连所述自适应均衡器中的至少一些的控制逻辑，以及控制机制， 根据不同的MDPE，配置至少一些自适应均衡器和控制逻辑。

公开(公告)号：US20090008235A1

公开(公告)日：2009-01-08

申请号：US12116339

申请日：2008-05-07

申请人： Manish Goel ,  Chetan Prakash Mittal

发明人： Manish Goel ,  Chetan Prakash Mittal

IPC分类号： B01D3/14 ,  B01D61/00

CPC分类号： B01D3/145 ,  B01D3/002 ,  B01D3/14 ,  B01D61/025 ,  B01D61/027 ,  B01D61/145 ,  B01D61/147 ,  B01D61/362 ,  B01D61/58

摘要： A system and process that are a hybrid of distillation and membrane separations offers a highly efficient means of separating a fluid feed mixture into organic, solid, and aqueous components. The distillation section is followed by two membrane separation sections operated in parallel, with the distillation section separating the feed mixture into an organics-rich fraction and an organics-depleted and solids-rich fraction. One membrane section operates on the organics-rich fraction and separates it into a more organics-rich sub-fraction and a water-rich, organics-depleted sub-fraction, while the other membrane section operates on the organics-depleted, solids-rich fraction from the distillation section and separates it into a solids-rich sub-fraction and a solids-depleted, water-rich sub-fraction.

摘要翻译： 作为蒸馏和膜分离的混合物的系统和方法提供了将流体进料混合物分离成有机，固体和水性组分的高效手段。 蒸馏段之后是两个平行操作的膜分离段，蒸馏段将进料混合物分离成富有机物部分和富有机物的富含部分。 一个膜段用于富有机物部分，并将其分离成更富有机物的亚馏分和富含水的富有机物的亚馏分，而另一个膜部分对有机物贫乏的固体富含 馏分从蒸馏部分分离成富含固体的亚馏分和固体贫乏的富水子馏分。

公开(公告)号：US07324614B2

公开(公告)日：2008-01-29

申请号：US10322874

申请日：2002-12-18

申请人： Seok-Jun Lee ,  Manish Goel

发明人： Seok-Jun Lee ,  Manish Goel

IPC分类号： H04D1/00 ,  H03M13/03

CPC分类号： H03M13/3961 ,  H03M13/395 ,  H03M13/41

摘要： A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.

摘要翻译： 分支度量复制方法大大减少了互连延迟。 分支度量复制方法对于实现针对FPGA应用的高速基数-4维特比解码器特别有用。 解码器包括多个分支度量计算单元（BMCU），至少一个具有多个单元的加法比较选择单元（ACSU）和幸存路径存储单元（SMU）。 多个BMCU，至少一个ACSU和SMU被配置为实现解码器。

公开(公告)号：US20070283215A1

公开(公告)日：2007-12-06

申请号：US11744357

申请日：2007-05-04

申请人： Yuming Zhu ,  Yanni Chen ,  Dale E. Hocevar ,  Manish Goel

发明人： Yuming Zhu ,  Yanni Chen ,  Dale E. Hocevar ,  Manish Goel

IPC分类号： H03M13/00

CPC分类号： H03M13/1111

摘要： A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.

摘要翻译： 本文描述了用于降低奇偶校验器的复杂度的方法和系统。 在至少一些优选实施例中，奇偶校验解码器包括列存储单元和耦合到列存储单元的一个或多个对准单元。 列存储单位超出排列单位。

公开(公告)号：US20070113161A1

公开(公告)日：2007-05-17

申请号：US11557208

申请日：2006-11-07

申请人： Srinivas Lingam ,  Seok-Jun Lee ,  Anuj Batra ,  Manish Goel

发明人： Srinivas Lingam ,  Seok-Jun Lee ,  Anuj Batra ,  Manish Goel

IPC分类号： H03M13/03

CPC分类号： H03M13/4107 ,  H03M13/395 ,  H03M13/4169

摘要： A Viterbi decoder includes a branch metric unit for generating branch metrics between two states at two different time periods, a traceback unit, a traceback memory and an add-compare-select circuit. The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a plurality of branch metrics from the branch metric unit and a plurality of pre-calculated path metrics, where at least one of the add-compare-select sub-circuits receives a set of pre-calculated path metrics from another one of the add-compare-select sub-circuits.

摘要翻译： 维特比解码器包括用于在两个不同时间段的两个状态之间产生分支度量的分支度量单位，追溯单元，回溯存储器和加法比较选择电路。 加法比较选择电路包括多个级联加法比较选择子电路，每个加法比较选择子电路响应于来自分支度量单位的多个分支度量而计算路径度量，并且多个 预先计算的路径度量，其中至少一个加法比较选择子电路从另一个加法比较选择子电路接收一组预先计算的路径度量。

公开(公告)号：US20060104393A1

公开(公告)日：2006-05-18

申请号：US10992404

申请日：2004-11-17

申请人： Michael DiRenzo ,  David Magee ,  Manish Goel

发明人： Michael DiRenzo ,  David Magee ,  Manish Goel

IPC分类号： H04L27/06

CPC分类号： H04L7/042 ,  H04B1/708 ,  H04B1/7093

摘要： The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted streams, where P is at least two. In one embodiment, the packet detector includes a correlation unit coupled to the single receive antenna and configured to provide a correlation function based on P acquisition fields corresponding to the P concurrently transmitted streams. Additionally, the packet detector also includes a pseudo-magnitude calculator coupled to the correlation unit and configured to calculate a packet detection metric based on the correlation function.

摘要翻译： 本发明提供了一种与用于P并发传输流的接收天线的基于分组的无线接收机一起使用的分组检测器，其中P是至少两个。 在一个实施例中，分组检测器包括耦合到单个接收天线的相关单元，并且被配置为基于与P个同时发送的流相对应的P采集字段来提供相关函数。 另外，分组检测器还包括耦合到相关单元并被配置为基于相关函数计算分组检测度量的伪幅度计算器。

公开(公告)号：US20050289253A1

公开(公告)日：2005-12-29

申请号：US10877587

申请日：2004-06-24

申请人： Samantha Edirisooriya ,  Joseph Murray ,  Gregory Tse ,  Vishram Sarurkar ,  Manish Goel

发明人： Samantha Edirisooriya ,  Joseph Murray ,  Gregory Tse ,  Vishram Sarurkar ,  Manish Goel

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A method and apparatus for a multi-function direct memory access core are described. In one embodiment, the method includes the reading of a direct memory access (DMA) descriptor having associated DMA data to identify at least one micro-command. Once the micro-command is identified, the DMA data is processed according to the micro-command during DMA transfer of the data. In one embodiment, a DMA engine performs an operation on the DMA data in transit within the DMA controller according to the identified micro-command. Hence, by defining a primitive set of micro-commands, the DMA engine within, for example, an input/output (I/O) controller hub (ICH), can be used to perform a large number of complex operations on data when data is passing through the ICH without introducing latency into the DMA transfer. Other embodiments are described and claimed.

摘要翻译： 描述了用于多功能直接存储器存取核心的方法和装置。 在一个实施例中，该方法包括读取具有相关DMA数据的直接存储器访问（DMA）描述符，以识别至少一个微指令。 一旦识别了微型命令，在DMA传输数据期间，根据微指令对DMA数据进行处理。 在一个实施例中，DMA引擎根据所识别的微指令对DMA控制器内的DMA数据执行操作。 因此，通过定义基本的微指令集，例如在输入/输出（I / O）控制器集线器（ICH）内的DMA引擎可用于对数据执行大量的复杂操作 正在通过ICH，而不会在DMA传输中引入延迟。 描述和要求保护其他实施例。

公开(公告)号：US20050170831A1

公开(公告)日：2005-08-04

申请号：US10929705

申请日：2004-08-30

申请人： David Magee ,  Manish Goel ,  Michael DiRenzo

发明人： David Magee ,  Manish Goel ,  Michael DiRenzo

IPC分类号： H04B7/08 ,  H04Q7/00

CPC分类号： H04B7/0811

摘要： A preamble frequency switching design technique for frequency switching the training symbols within the preamble associated with a MIMO communication system ensures that data throughput is optimized.

摘要翻译： 用于频率切换与MIMO通信系统相关的前导码内的训练符号的前导码频率切换设计技术确保数据吞吐量被优化。

公开(公告)号：US10949646B2

公开(公告)日：2021-03-16

申请号：US16399519

申请日：2019-04-30

申请人： Manish Goel ,  Yuming Zhu

发明人： Manish Goel ,  Yuming Zhu

IPC分类号： G06K9/00 ,  G06K9/62 ,  G06T7/73 ,  G06T7/579

摘要： A method of performing an iterative bundle adjustment for an imaging device is described. The method comprising implementing a plurality of functions in performing a bundle adjustment. Predetermined functions of the plurality of functions may be started using a processor for a second iteration in parallel with a first iteration of the plurality of functions. A result of the predetermined functions started during the first iteration may be used in a second iteration. An output of the bundle adjustment may then be generated for successive iterations.