公开(公告)号：US20080126688A1

公开(公告)日：2008-05-29

申请号：US11929417

申请日：2007-10-30

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F9/455 ,  G06F12/00

CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

公开(公告)号：US20080056014A1

公开(公告)日：2008-03-06

申请号：US11762010

申请日：2007-06-12

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

公开(公告)号：US20080028137A1

公开(公告)日：2008-01-31

申请号：US11828182

申请日：2007-07-25

申请人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G06F13/28

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40618

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时 基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出

公开(公告)号：US08566516B2

公开(公告)日：2013-10-22

申请号：US11929631

申请日：2007-10-30

申请人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G06F13/12

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.

摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时 基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出。

公开(公告)号：US20130132661A1

公开(公告)日：2013-05-23

申请号：US13620645

申请日：2012-09-14

申请人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G11C11/406

CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  Y02D10/14

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时 基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出

公开(公告)号：US08631193B2

公开(公告)日：2014-01-14

申请号：US13473827

申请日：2012-05-17

申请人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

发明人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

摘要翻译： 本发明的一个实施例提出了一种抽象存储器子系统，其包括抽象存储器，每个存储器子系统可被配置为将存储器相关特性呈现到存储器系统接口上。 该特性可以通过逻辑信号或协议交换在存储器系统接口上呈现，并且特征可以包括地址空间，协议，存储器类型，功率管理规则，多个流水线级中的任何一个或多个， 多个银行，映射到物理银行，多个等级，定时特征，地址解码选项，总线周转时间参数，附加信号断言，子秩，多个平面或其他存储器 - 相关特征 一些实施例包括智能寄存器装置和/或智能缓冲器装置。 所公开的子系统的一个优点是可以优化存储器性能，而不管底层存储器硬件设备使用的特定协议。

公开(公告)号：US20080082763A1

公开(公告)日：2008-04-03

申请号：US11538041

申请日：2006-10-02

申请人： Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G06F13/00

CPC分类号： G06F17/5009 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4093

摘要： An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

摘要翻译： 提供了一种用于与多个物理存储器电路通信的装置和方法。 在使用中，模拟至少一个虚拟存储器电路，其中这种虚拟存储器电路的至少一个方面（例如，功率相关方面等）与至少一个物理存储器电路的至少一个方面不同 。 此外，在各种实施例中，这种模拟可以由系统（或其组件），接口电路等执行

公开(公告)号：US20130007399A1

公开(公告)日：2013-01-03

申请号：US13615008

申请日：2012-09-13

申请人： Michael John Sebastian Smith ,  Daniel L. Rosenband ,  David T. Wang ,  Suresh Natarajan Rajan

发明人： Michael John Sebastian Smith ,  Daniel L. Rosenband ,  David T. Wang ,  Suresh Natarajan Rajan

IPC分类号： G06F12/00

CPC分类号： G06F1/08

摘要： A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.

摘要翻译： 提供了一种用于调整与存储器系统相关联的信号的定时的系统和方法。 提供存储器控制器。 另外，提供至少一个存储器模块。 此外，提供至少一个接口电路，所述接口电路能够调整与所述存储器控制器和所述至少一个存储器模块中的一个或多个相关联的信号的定时。

公开(公告)号：US08972673B2

公开(公告)日：2015-03-03

申请号：US13620601

申请日：2012-09-14

申请人： Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G06F17/50 ,  G06F12/08 ,  G11C11/4093 ,  G11C11/4074 ,  G11C5/14

CPC分类号： G06F17/5009 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4093

摘要： An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

摘要翻译： 提供了一种用于与多个物理存储器电路通信的装置和方法。 在使用中，模拟至少一个虚拟存储器电路，其中这种虚拟存储器电路的至少一个方面（例如，功率相关方面等）与至少一个物理存储器电路的至少一个方面不同 。 此外，在各种实施例中，这种模拟可以由系统（或其组件），接口电路等执行

公开(公告)号：US20130103377A1

公开(公告)日：2013-04-25

申请号：US13620601

申请日：2012-09-14

申请人： Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4093

摘要： An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

摘要翻译： 提供了一种用于与多个物理存储器电路通信的装置和方法。 在使用中，模拟至少一个虚拟存储器电路，其中这种虚拟存储器电路的至少一个方面（例如，功率相关方面等）与至少一个物理存储器电路的至少一个方面不同 。 此外，在各种实施例中，这种模拟可以由系统（或其组件），接口电路等执行